Single event transients in digital CMOS—A review
V Ferlet-Cavrois, LW Massengill… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
The creation of soft errors due to the propagation of single event transients (SETs) is a
significant reliability challenge in modern CMOS logic. SET concerns continue to be …
significant reliability challenge in modern CMOS logic. SET concerns continue to be …
Physics of multiple-node charge collection and impacts on single-event characterization and soft error rate prediction
Physical mechanisms of single-event effects that result in multiple-node charge collection or
charge sharing are reviewed and summarized. A historical overview of observed circuit …
charge sharing are reviewed and summarized. A historical overview of observed circuit …
Modeling single event transients in advanced devices and ICs
The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs)
was predicted for the first time by Wallmark and Marcus in the early 60's and was confirmed …
was predicted for the first time by Wallmark and Marcus in the early 60's and was confirmed …
Impact of technology scaling on SRAM soft error rates
I Chatterjee, B Narasimham… - … on Nuclear Science, 2014 - ieeexplore.ieee.org
Soft error rates for triple-well and dual-well SRAM circuits over the past few technology
generations have shown an apparently inconsistent behavior. This work compares the …
generations have shown an apparently inconsistent behavior. This work compares the …
Layout technique for single-event transient mitigation via pulse quenching
NM Atkinson, AF Witulski, WT Holman… - … on Nuclear Science, 2011 - ieeexplore.ieee.org
Layout Technique for Single-Event Transient Mitigation via Pulse Quenching Page 1 IEEE
TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 3, JUNE 2011 885 Layout Technique …
TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 3, JUNE 2011 885 Layout Technique …
[PDF][PDF] Technology scaling and soft error reliability
LW Massengill, BL Bhuva… - 2012 IEEE …, 2012 - reliablemicrosystems.com
Technology Scaling and Soft Error Reliability Page 1 Technology Scaling and Soft Error
Reliability Lloyd W. Massengill Professor, Department of Electrical Engineering and Computer …
Reliability Lloyd W. Massengill Professor, Department of Electrical Engineering and Computer …
Scaling trends in SET pulse widths in sub-100 nm bulk CMOS processes
Digital single-event transient (SET) measurements in a bulk 65-nm process are compared to
transients measured in 130-nm and 90-nm processes. The measured SET widths are …
transients measured in 130-nm and 90-nm processes. The measured SET widths are …
Single-event transient modeling in a 65-nm bulk CMOS technology based on multi-physical approach and electrical simulations
This paper presents a SET predictive methodology based on coupled MUSCA SEP3 and
electrical simulations (CADENCE tool). The method is validated by SET measurements on …
electrical simulations (CADENCE tool). The method is validated by SET measurements on …
Layout-based modeling and mitigation of multiple event transients
Radiation-induced multiple event transients (METs) are expected to become more frequent
than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a …
than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a …
SEU prediction from SET modeling using multi-node collection in bulk transistors and SRAMs down to the 65 nm technology node
A new methodology of prediction for SEU is proposed based on SET modeling. The
modeling of multi-node charge collection is performed using the ADDICT model for …
modeling of multi-node charge collection is performed using the ADDICT model for …