An ultra-low-power, 2 7-1 PRBS generator with four, appropriately delayed, parallel output
streams was designed. It was fabricated in a 150-GHz f T SiGe BiCMOS technology and …

This brief presents a compact low-power programmable multi-pattern pseudo-random binary
sequence (PRBS) generator. It is capable of producing 2 7-1, 2 15-1, 2 23-1 and 2 31-1 test …

A 2/sup 31/-1 pseudorandom binary sequence (PRBS) generator with adjustable output
data rates up to 80 Gb/s is reported in a production 130-nm BiCMOS process with 150-GHz …

This paper presents two monolithic pseudorandom bit sequence (PRBS) generators. One
circuit uses a seven-stage shift register operating with a half-rate clock and provides output …

A bit error rate tester and a pseudo random bit sequences (PRBS) generator thereof are
provided. The bit error rate tester includes a transmitter PRBS generator, a master PRBS …

In post-silicon testing and validation of circuit functionality, an effective IO stress pattern can
identify bugs quickly and provide adequate test coverage. A lot of work has been done to …

With increasing of clock rate and routing density, the problem of signal integrity in high-
speed parallel links is becoming increasingly serious. Hence, the design of an effective …

This paper presents the design of a programmable PRBS generator and a BER tester
according to CCITT recommendations. Implemented in a parallel feedback configuration …

This paper presents the design of a low power programmable PRBS generator and a low
noise clock multiplier unit (CMU) for 10 Gbps serdes applications. The PRBS generator is …

This paper presents the design of a 12 Gbps multi-lane 2 31-1 pseudo-random binary
sequence (PRBS) generator in 0.18 μ m TSMC process. The design incorporates a …