A 60 mW per Lane, 4$, times, $23-Gb/s 2$^ 7-$1 PRBS Generator
E Laskin, SP Voinigescu - IEEE Journal of Solid-State Circuits, 2006 - ieeexplore.ieee.org
An ultra-low-power, 2 7-1 PRBS generator with four, appropriately delayed, parallel output
streams was designed. It was fabricated in a 150-GHz f T SiGe BiCMOS technology and …
streams was designed. It was fabricated in a 150-GHz f T SiGe BiCMOS technology and …
A 15-Gb/s 0.0037-mm² 0.019-pJ/bit full-rate programmable multi-pattern pseudo-random binary sequence generator
This brief presents a compact low-power programmable multi-pattern pseudo-random binary
sequence (PRBS) generator. It is capable of producing 2 7-1, 2 15-1, 2 23-1 and 2 31-1 test …
sequence (PRBS) generator. It is capable of producing 2 7-1, 2 15-1, 2 23-1 and 2 31-1 test …
An 80-Gb/s 2/sup 31/-1 pseudorandom binary sequence generator in SiGe BiCMOS technology
TO Dickson, E Laskin, I Khalid… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
A 2/sup 31/-1 pseudorandom binary sequence (PRBS) generator with adjustable output
data rates up to 80 Gb/s is reported in a production 130-nm BiCMOS process with 150-GHz …
data rates up to 80 Gb/s is reported in a production 130-nm BiCMOS process with 150-GHz …
100-Gb/s 2/sup 7/-1 and 54-Gb/s 2/sup 11/-1 PRBS generators in SiGe bipolar technology
H Knapp, M Wurzer, W Perndl… - IEEE journal of solid …, 2005 - ieeexplore.ieee.org
This paper presents two monolithic pseudorandom bit sequence (PRBS) generators. One
circuit uses a seven-stage shift register operating with a half-rate clock and provides output …
circuit uses a seven-stage shift register operating with a half-rate clock and provides output …
Bit error rate tester and pseudo random bit sequences generator thereof
WZ Chen, GS Huang - US Patent 7,486,725, 2009 - Google Patents
A bit error rate tester and a pseudo random bit sequences (PRBS) generator thereof are
provided. The bit error rate tester includes a transmitter PRBS generator, a master PRBS …
provided. The bit error rate tester includes a transmitter PRBS generator, a master PRBS …
Comparison of hardware based and software based stress testing of memory IO interface
B Querbach, S Puligundla, D Becerra… - 2013 IEEE 56th …, 2013 - ieeexplore.ieee.org
In post-silicon testing and validation of circuit functionality, an effective IO stress pattern can
identify bugs quickly and provide adequate test coverage. A lot of work has been done to …
identify bugs quickly and provide adequate test coverage. A lot of work has been done to …
An Efficient Stress Pattern Based on VMRQ-PRBS for DDR Training
X Chu, J Wang, K Li, R Wang… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
With increasing of clock rate and routing density, the problem of signal integrity in high-
speed parallel links is becoming increasingly serious. Hence, the design of an effective …
speed parallel links is becoming increasingly serious. Hence, the design of an effective …
A parallel multi-pattern PRBS generator and BER tester for 40/sup+/Gbps Serdes applications
WZ Chen, GS Huang - Proceedings of 2004 IEEE Asia-Pacific …, 2004 - ieeexplore.ieee.org
This paper presents the design of a programmable PRBS generator and a BER tester
according to CCITT recommendations. Implemented in a parallel feedback configuration …
according to CCITT recommendations. Implemented in a parallel feedback configuration …
A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications
WZ Chen, GS Huang - 2006 IEEE International Symposium on …, 2006 - ieeexplore.ieee.org
This paper presents the design of a low power programmable PRBS generator and a low
noise clock multiplier unit (CMU) for 10 Gbps serdes applications. The PRBS generator is …
noise clock multiplier unit (CMU) for 10 Gbps serdes applications. The PRBS generator is …
High-speed circuits for a multi-lane 12 Gbps CMOS PRBS generator
S Bommalingaiahnapallya, KJ Sham… - … on Circuits and …, 2007 - ieeexplore.ieee.org
This paper presents the design of a 12 Gbps multi-lane 2 31-1 pseudo-random binary
sequence (PRBS) generator in 0.18 μ m TSMC process. The design incorporates a …
sequence (PRBS) generator in 0.18 μ m TSMC process. The design incorporates a …