The occurrence of a single event with a multiple-node upset is likely to increase significantly
in nanoscale CMOS due to reduced device size and power supply voltage scaling. This …

This paper presents and analyzes a high performance latch tolerating single event upsets
(SEU) in 45 nm CMOS technology. The internal nodes of the latch are immune to SEUs by …

In Monte Carlo particle transport codes, it is often important to adjust reaction cross-sections
to reduce the variance of calculations of relatively rare events, in a technique known as non …

Radiation-induced soft errors have become a key challenge in advanced commercial
electronic components and systems. We present the results of a soft error rate (SER) …

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and
HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs) …

In this paper, we propose a novel hardened latch to mitigate the SEU. The combination of
the circuit structure and layout placement is adopted to enhance the multiple nodes upset …

Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-
node upset. This paper presents a novel memory cell design as variant of the DICE cell (that …

In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are
proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully …

The sensitivity of nanometric technologies, to electron induced single-event upset (SEU), is
analyzed thanks to some microdosimetry calculations performed into nanoscale volumes …

Experimental neutron single-event error rates of 28-and 40-nm bulk CMOS hardened flip-
flops are compared to various hardened flip-flop designs in literature. Using published 45 …