Rl-sizer: Vlsi gate sizing for timing optimization using deep reinforcement learning
Gate sizing for timing optimization is performed extensively throughout electronic design
automation (EDA) flows. However, increasing design sizes and time-to-market pressure …
automation (EDA) flows. However, increasing design sizes and time-to-market pressure …
Doomed run prediction in physical design by exploiting sequential flow and graph learning
Modern designs are increasingly reliant on physical design (PD) tools to derive full
technology scaling benefits of Moore's Law. Designers often perform power, performance …
technology scaling benefits of Moore's Law. Designers often perform power, performance …
Eco-gnn: Signoff power prediction using graph neural networks with subgraph approximation
Modern electronic design automation flows depend on both implementation and signoff
tools to perform timing-constrained power optimization through Engineering Change Orders …
tools to perform timing-constrained power optimization through Engineering Change Orders …
On advancing physical design using graph neural networks
As modern Physical Design (PD) algorithms and methodologies evolve into the post-Moore
era with the aid of machine learning, Graph Neural Networks (GNNs) are becoming …
era with the aid of machine learning, Graph Neural Networks (GNNs) are becoming …
A graph neural network method for fast ECO leakage power optimization
K Wang, P Cao - 2022 27th Asia and South Pacific Design …, 2022 - ieeexplore.ieee.org
In modern design, engineering change order (ECO) is often utilized to perform power
optimization including gate-sizing and Vth-assignments, which is efficient but highly timing …
optimization including gate-sizing and Vth-assignments, which is efficient but highly timing …