Semiconductor device and a method for fabricating the same
CM Hsu, T Chih-Pin, JH Chen, KY Hsu… - US Patent …, 2018 - Google Patents
In a method of manufacturing a semiconductor device, a first contact hole is formed in one or
more dielectric layers disposed over a source/drain region or a gate electrode. An adhesive …
more dielectric layers disposed over a source/drain region or a gate electrode. An adhesive …
Dual metal via for contact resistance reduction
CL Cheng, YY Chen - US Patent 10,651,292, 2020 - Google Patents
A semiconductor device includes an active region over a substrate; a first cobalt-containing
feature disposed over the active region; a conductive cap disposed over and in physical …
feature disposed over the active region; a conductive cap disposed over and in physical …
Semiconductor device including self-aligned gate structure and improved gate spacer topography
VS Basker, T Yamashita - US Patent 9,425,105, 2016 - Google Patents
BACKGROUND The present invention relates to semiconductor devices, and more
specifically, to three-dimensional (3D) semicon ductor devices. Field effect transistors (FETs) …
specifically, to three-dimensional (3D) semicon ductor devices. Field effect transistors (FETs) …
Methods of producing fully self-aligned vias and contacts
Y Zhang, R Freed, NK Ingle, HY Hwang… - US Patent …, 2020 - Google Patents
Methods and apparatus to form fully self-aligned vias are described. First conductive lines
are recessed in a first insulating layer on a substrate. A first metal film is formed in the …
are recessed in a first insulating layer on a substrate. A first metal film is formed in the …
Selective removal process to create high aspect ratio fully self-aligned via
AB Mullick, M Sachan, H Ren, S Srinivasan… - US Patent …, 2020 - Google Patents
Apparatuses and methods to provide a fully self-aligned via are described. Some
embodiments of the disclosure utilize a cap layer to protect an insulating layer in order to …
embodiments of the disclosure utilize a cap layer to protect an insulating layer in order to …
Methods of producing self-aligned vias
Y Zhang, R Freed, NK Ingle, HYD Hwang… - US Patent …, 2020 - Google Patents
2 () 16/()() 56 () 74 A 1 2/2 () 16 Ng 7.541. 297 B2 6/2009 Mallick et al. 2 () 16/00561 () 4 A 1
2/20 16 Bouche et al. 7985977 B2 7/2011 Gogoi et al. 2 () 16/()() 687 1 () A 1 3/2 () 16 VV …
2/20 16 Bouche et al. 7985977 B2 7/2011 Gogoi et al. 2 () 16/()() 687 1 () A 1 3/2 () 16 VV …
Wet etch removal of Ru selective to other metals
BD Briggs, CB Peethala, DL Rath - US Patent 10,242,909, 2019 - Google Patents
(57) ABSTRACT A method for forming a conductive structure for a semicon ductor device
includes depositing a barrier layer in a trench formed in a dielectric material and forming an …
includes depositing a barrier layer in a trench formed in a dielectric material and forming an …
Method for creating a fully self-aligned via
R Freed, U Mitra, S Natarajan - US Patent 10,892,187, 2021 - Google Patents
Apparatuses and methods to provide a fully self-aligned via are described. Some
embodiments of the disclosure provide an electronic device having a bridging via between a …
embodiments of the disclosure provide an electronic device having a bridging via between a …
Low resistance metal contacts to interconnects
SM Gates, GM Fritz, EA Joseph, TA Spooner - US Patent 9,786,550, 2017 - Google Patents
A semiconductor device and a method of fabricating a contact to interface with an
interconnect in a semiconductor device are described. The device includes a dielectric layer …
interconnect in a semiconductor device are described. The device includes a dielectric layer …
Vias for cobalt-based interconnects and methods of fabrication thereof
YJ Chang, MY Hsieh, HF Chen, KH Pan - US Patent 10,553,481, 2020 - Google Patents
Interconnect structures and corresponding techniques for forming the interconnect structures
are disclosed herein. An exemplary interconnect structure includes a conductive feature that …
are disclosed herein. An exemplary interconnect structure includes a conductive feature that …