Dielectric breakdown of oxide films in electronic devices

A Padovani, P La Torraca, J Strand, L Larcher… - Nature Reviews …, 2024 - nature.com
Dielectric breakdown is a sudden and catastrophic increase in the conductivity of an
insulator caused by electrical stress. It is one of the major reliability issues in electronic …

Resistive switching in HfO2 based valence change memories, a comprehensive 3D kinetic Monte Carlo approach

S Aldana, P García-Fernández… - Journal of Physics D …, 2020 - iopscience.iop.org
A simulation study has been performed to analyze resistive switching (RS) phenomena in
valence change memories (VCM) based on a HfO 2 dielectric. The kernel of the simulation …

Microscopic modeling of electrical stress-induced breakdown in poly-crystalline hafnium oxide dielectrics

L Vandelli, A Padovani, L Larcher… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
We present a quantitative physical model describing degradation of poly-crystalline HfO 2
dielectrics subjected to electrical stress culminating in the dielectric breakdown (BD). The …

Charge Transport and Degradation in HfO2 and HfOx Dielectrics

A Padovani, L Larcher, G Bersuker… - IEEE electron device …, 2013 - ieeexplore.ieee.org
We combine experiments and simulations to investigate leakage current and breakdown
(BD) in stoichiometric and sub-stoichiometric hafnium oxides. Using charge-transport …

High-κ dielectric breakdown in nanoscale logic devices–Scientific insight and technology impact

N Raghavan, KL Pey, K Shubhakar - Microelectronics Reliability, 2014 - Elsevier
Dielectric breakdown is one of the key failure mechanisms in front-end silicon-based
complementary metal oxide semiconductor (CMOS) technology. With the advent of HfO 2 …

Modeling of emerging resistive switching based memory cells

A Makarov - 2014 - repositum.tuwien.at
For many decades charge-based memory (eg dynamic random access memory (DRAM),
flash memory, etc.) technologies have been successfully scaled down to achieve higher …

A simulation framework for modeling charge transport and degradation in high-k stacks

L Larcher, A Padovani, L Vandelli - Journal of Computational Electronics, 2013 - Springer
In this paper we present a comprehensive physical model that describes charge transport
and degradation phenomena in high-k stacks. The physical mechanisms are modeled using …

Modeling of the forming operation in HfO2-based resistive switching memories

L Vandelli, A Padovani, G Bersuker… - 2011 3rd IEEE …, 2011 - ieeexplore.ieee.org
This paper presents a novel physical description of the forming process in HfO 2-based
resistive switching memory devices (RRAM). By taking into consideration a grain boundary …

Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-κ gate dielectric stacks

N Raghavan, KL Pey, K Shubhakar… - 2012 IEEE …, 2012 - ieeexplore.ieee.org
Grain boundary (GB) microstructural defects in polycrystalline high-? dielectric thin films may
cause localized non-random trap generation during the percolation breakdown (BD) …

Physical analysis of breakdown in high-κ/metal gate stacks using TEM/EELS and STM for reliability enhancement

KL Pey, N Raghavan, X Wu, W Liu, X Li… - Microelectronic …, 2011 - Elsevier
In this invited paper, we demonstrate how physical analysis techniques that are commonly
used in integrated circuits failure analysis can be applied to detect the failure defects …