Soft error reliability evaluation of nanoscale logic circuits in the presence of multiple transient faults

S Cai, B He, W Wang, P Liu, F Yu, L Yin, B Li… - Journal of Electronic …, 2020 - Springer
Radiation-induced single transient faults (STFs) are expected to evolve into multiple
transient faults (MTFs) at nanoscale CMOS technology nodes. For this reason, the reliability …

A novel trust evaluation method for logic circuits in IoT applications based on the E-PTM model

J Xiao, J Jiang, X Li, Y Huang, X Yang, Z Shi… - IEEE Access, 2018 - ieeexplore.ieee.org
The increase in the reliability requirements of integrated circuits applied in diverse smart
sensing devices and the increase in the cost of test generation and fault simulation have …

Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits

MI Bandan, S Pagliarini, J Mathew… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
State-of-the-art commercial placement tools have as goals to optimize area, timing, and
power. Over the years, several reliability oriented placement strategies have been proposed …

A novel gate grading approach for soft error tolerance in combinational circuits

MS Ansari, A Mahani, J Han… - 2016 IEEE Canadian …, 2016 - ieeexplore.ieee.org
Continuous reduction in the minimum feature size of semiconductor devices and the supply
voltages in advanced VLSI logic circuits has made those circuits more susceptible to soft …

[引用][C] Avaliação de confiabilidade considerando falhas transientes do tipo Single Event Transient

[引用][C] A weighted averaging method for signal probabilityof logic circuit combined with reconvergent fan-out structures () Share

X Jie, M Weifeng, W Lee, S Zhanhui