[图书][B] Security in RFID and sensor networks
P Kitsos - 2016 - taylorfrancis.com
In the past several years, there has been an increasing trend in the use of Radio Frequency
Identification (RFID) and Wireless Sensor Networks (WSNs) as well as in the integration of …
Identification (RFID) and Wireless Sensor Networks (WSNs) as well as in the integration of …
Systolic and Super-Systolic Multipliers for Finite Field Based on Irreducible Trinomials
PK Meher - IEEE Transactions on Circuits and Systems I …, 2008 - ieeexplore.ieee.org
Novel systolic and super-systolic architectures are presented for polynomial basis
multiplication over GF (2 m) based on irreducible trinomials. By suitable cut-set retiming, we …
multiplication over GF (2 m) based on irreducible trinomials. By suitable cut-set retiming, we …
Bit-serial and bit-parallel montgomery multiplication and squaring over GF (2^ m)
A Hariri, A Reyhani-Masoleh - IEEE Transactions on Computers, 2009 - ieeexplore.ieee.org
Multiplication and squaring are main finite field operations in cryptographic computations
and designing efficient multipliers and squarers affect the performance of cryptosystems. In …
and designing efficient multipliers and squarers affect the performance of cryptosystems. In …
On Efficient Implementation of Accumulation in Finite Field Over and its Applications
PK Meher - IEEE Transactions on very large scale integration …, 2009 - ieeexplore.ieee.org
Finite field accumulation is the simplest of all the finite field operations, but at the same time,
it is one of the most frequently encountered operations in finite field arithmetic. In this paper …
it is one of the most frequently encountered operations in finite field arithmetic. In this paper …
LFSR-Based Bit-Serial Multipliers Using Irreducible Trinomials
JL Imana - IEEE Transactions on Computers, 2020 - ieeexplore.ieee.org
In this article, a new architecture of bit-serial polynomial basis (PB) multipliers over the
binary extension field GF (2 m) generated by irreducible trinomials is presented. Bit-serial …
binary extension field GF (2 m) generated by irreducible trinomials is presented. Bit-serial …
Systolic and non-systolic scalable modular designs of finite field multipliers for Reed–Solomon codec
PK Meher - IEEE transactions on very large scale integration …, 2009 - ieeexplore.ieee.org
In this paper, we present efficient algorithms for modular reduction to derive novel systolic
and non-systolic architectures for polynomial basis finite field multipliers over GF (2 m) to be …
and non-systolic architectures for polynomial basis finite field multipliers over GF (2 m) to be …
Input–output scheduling and control for efficient FPGA realization of digit-serial multiplication over generic binary extension fields
In this paper, we propose an energy-efficient design of architecture for digit-serial
multiplication over generic GF (2 m), which could be used for different fields as and when …
multiplication over generic GF (2 m), which could be used for different fields as and when …
Digit-serial structures for the shifted polynomial basis multiplication over binary extension fields
A Hariri, A Reyhani-Masoleh - Arithmetic of Finite Fields: 2nd International …, 2008 - Springer
Finite field multiplication is one of the most important operations in the finite field arithmetic.
Recently, a variation of the polynomial basis, which is known as the shifted polynomial …
Recently, a variation of the polynomial basis, which is known as the shifted polynomial …
Throughput/area efficient implementation of scalable polynomial basis multiplication
B Rashidi - Journal of Hardware and Systems Security, 2020 - Springer
In this paper, a scalable throughput/area efficient hardware implementation of polynomial
basis multiplication based on a digit-digit structure is presented. To compute multiplication …
basis multiplication based on a digit-digit structure is presented. To compute multiplication …
Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2 m ) Using Progressive Multiplier Reduction
We present low area and low power semi-systolic array architectures for polynomial basis
multiplication over GF (2 m) using Progressive Multiplier Reduction Technique (PMR) …
multiplication over GF (2 m) using Progressive Multiplier Reduction Technique (PMR) …