A 0.14-to-0.29-pJ/bit 14-GBaud/s trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit in 28-nm CMOS
This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit
supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover …
supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover …
A 4-Bit 4GS/s differential current steering DAC for 16-bit PAM transmitter in 45-nm CMOS technology
This paper presents a design of 4 bit differential current steering (DCS) DAC as a part of
16bit PAM transmitter (4-b/symbol) for achieving 4Gb/s data rate in 45-nm CMOS …
16bit PAM transmitter (4-b/symbol) for achieving 4Gb/s data rate in 45-nm CMOS …
A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI
F Celik, A Akkaya, Y Leblebici - Microelectronics Journal, 2021 - Elsevier
This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-
terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The …
terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The …
A 125 m-Pitch-Matched Transceiver ASIC With Micro-Beamforming ADC and Multi-Level Signaling for 3-D Transfontanelle Ultrasonography
P Guo, F Fool, ZY Chang, E Noothout… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
This article presents a pitch-matched transceiver application-specific integrated circuit
(ASIC) for a wearable ultrasound device intended for transfontanelle ultrasonography, which …
(ASIC) for a wearable ultrasound device intended for transfontanelle ultrasonography, which …
A 13.5-mW 10-Gb/s 4-PAM Serial Link Transmitter in 0.13- CMOS Technology
B Song, K Kim, J Lee, J Chung… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
A 13.5-mW 10-Gb/s four-level pulse-amplitude modulation (4-PAM) serial link transmitter is
presented. To improve the power efficiency, a voltage-mode 4-PAM driver is proposed. It …
presented. To improve the power efficiency, a voltage-mode 4-PAM driver is proposed. It …
A capacitor-DAC-based technique for pre-emphasis-enabled multilevel transmitters
This brief presents a capacitor digital-to-analog converter (DAC) based technique that is
suitable for pre-emphasis-enabled multilevel wireline transmitter design in voltage mode …
suitable for pre-emphasis-enabled multilevel wireline transmitter design in voltage mode …
A low-power 4-PAM transceiver using a dual-sampling technique for heterogeneous latency-sensitive network-on-chip
This brief presents a four-level pulse-amplitude modulation (4-PAM) transceiver for latency-
sensitive network-on-chip (NoC) applications. The proposed source-synchronous PAM …
sensitive network-on-chip (NoC) applications. The proposed source-synchronous PAM …
Design of a CML Transceiver With Self-Immunity to EMI in 0.18- m CMOS
GE Matig-a, MR Yuce… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This paper presents the design of an integrated current mode logic (CML) transceiver
system that demonstrates a superior robustness to electromagnetic interference (EMI). The …
system that demonstrates a superior robustness to electromagnetic interference (EMI). The …
A CMOS 7Gb/s, 4-PAM and 4-PWM, serial link transceiver
N Ghaderi, ZD Ghol, SR Fatemi - Analog integrated circuits and signal …, 2016 - Springer
This paper proposes a new multi level of amplitude and pulse width (PW) modulation
structure for a 7Gb/s serial link transceiver. This scheme can be implemented in 0.18 m …
structure for a 7Gb/s serial link transceiver. This scheme can be implemented in 0.18 m …
An adaptive edge decision feedback equalizer with 4PAM signalling
M Dolan, F Yuan - 2017 IEEE 60th International Midwest …, 2017 - ieeexplore.ieee.org
This paper presents an adaptive edge decision feedback equalizer (DFE) with 4PAM
signaling. Optimal DFE tap coefficients and threshold voltages for data recovery are …
signaling. Optimal DFE tap coefficients and threshold voltages for data recovery are …