Selection of initial states for formal verification
JAG Seawright, R Sathianathan, CG Gauthron… - US Patent …, 2008 - Google Patents
(21) Appl. No.: 10/340,500(57) ABSTRACT (22) Filed: Jan. 10, 2003 (51) Int. Cl. A computer
is programmed to automatically select a state or G06F 7/50(2006.01) a set of States of a …
is programmed to automatically select a state or G06F 7/50(2006.01) a set of States of a …
Reuse of learned information to simplify functional verification of a digital circuit
(57) ABSTRACT A computer is programmed in accordance with the invention to
automatically analyze a digital circuit, to check if the digital circuit can enter a target state …
automatically analyze a digital circuit, to check if the digital circuit can enter a target state …
Verification systems and methods
OA Petlin - US Patent App. 12/793,719, 2010 - Google Patents
BACKGROUND 0003. As hardware circuits increase in complexity, it is important that
integrated circuit designs are thoroughly tested for possible errors prior to fabrication …
integrated circuit designs are thoroughly tested for possible errors prior to fabrication …
Method of applying vertex based corrections to a semiconductor design
T Quaglio, M Millequant, C Tiphine - US Patent 10,534,255, 2020 - Google Patents
(57) ABSTRACT A method of geometry corrections to properly transfer semiconductor
designs on a wafer or a mask in nanometer scale processes is provided. In contrast with …
designs on a wafer or a mask in nanometer scale processes is provided. In contrast with …
Measure of analysis performed in property checking
(52) US Cl......... grgrrr. 71.6/4 will not be violated within a distance N from an initial state (58)
Field of Classification Search................ 71.6/4-6 from which the analysis started. Therefore, in …
Field of Classification Search................ 71.6/4-6 from which the analysis started. Therefore, in …
Accelerating high-level bounded model checking
(57) ABSTRACT An accelerated High-Level Bounded Model Checking method that
efficiently extracts high-level information from the model, uses that extracted information to …
efficiently extracts high-level information from the model, uses that extracted information to …
Debugging of counterexamples in formal verification
J Martensson - US Patent 8,103,999, 2012 - Google Patents
BACKGROUND This invention relates generally to formal verification of circuit designs, and
more particularly to debugging counter examples found in formal verification. As the …
more particularly to debugging counter examples found in formal verification. As the …
Formal verification coverage metrics for circuit design properties
ZE Hanna, PAM Franzen, RM Weber, HA Farah… - US Patent …, 2015 - Google Patents
(57) ABSTRACT A computer-implemented method and non-transitory com puter readable
medium for circuit design verification. Formal Verification is performed on a circuit design to …
medium for circuit design verification. Formal Verification is performed on a circuit design to …
Formal verification coverage metrics of covered events for circuit design properties
2005.0114805 A1 5/2005 Novakovsky et al. 2006, OO 10428 A1 1/2006 Rushby et al.
2007/0022394 A1 1/2007 Ghosh et al. 2007, 0180414 A1 8, 2007 Harer et al …
2007/0022394 A1 1/2007 Ghosh et al. 2007, 0180414 A1 8, 2007 Harer et al …
Measure of analysis performed in property checking
The amount of analysis performed in determining the validity of a property of a digital circuit
is measured concurrent With performance of the analysis, and provided as an output When …
is measured concurrent With performance of the analysis, and provided as an output When …