Bottom-up and top-down approaches for the design of neuromorphic processing systems: tradeoffs and synergies between natural and artificial intelligence
While Moore's law has driven exponential computing power expectations, its nearing end
calls for new avenues for improving the overall system performance. One of these avenues …
calls for new avenues for improving the overall system performance. One of these avenues …
Bottom-up and top-down neural processing systems design: Neuromorphic intelligence as the convergence of natural and artificial intelligence
While Moore's law has driven exponential computing power expectations, its nearing end
calls for new avenues for improving the overall system performance. One of these avenues …
calls for new avenues for improving the overall system performance. One of these avenues …
Static timing analysis of asynchronous bundled-data circuits
G Gimenez, A Cherkaoui, G Cogniard… - 2018 24th IEEE …, 2018 - ieeexplore.ieee.org
Self-timed circuits appear today as an attractive solution for designing robust and low-power
chips dedicated to smart sensing and Internet of Things (IoT) platforms. However, a massive …
chips dedicated to smart sensing and Internet of Things (IoT) platforms. However, a massive …
A low-power asynchronous RISC-V processor with propagated timing constraints method
Z Li, Y Huang, L Tian, R Zhu, S Xiao… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Over the past decade, the design of low-power processors is a primary requirement of
emerging applications, as Internet of Things (IoT) and neuromorphic chips. Therefore, there …
emerging applications, as Internet of Things (IoT) and neuromorphic chips. Therefore, there …
An efficient asynchronous circuits design flow with backward delay propagation constraint
L Zhou, S Xiao, H Wang, J Wang, Z Xu… - … , Automation & Test …, 2024 - ieeexplore.ieee.org
Asynchronous circuits have recently become more popular in Internet of Things (IoT) and
neural network chips because of their potential low power consumption. However, due to the …
neural network chips because of their potential low power consumption. However, due to the …
From signal transition graphs to timing closure: Application to bundled-data circuits
In this paper, an in-depth timing analysis of asynchronous bundled-data circuits is
presented. We leverage the controller Signal Transition Graph to extract and classify their …
presented. We leverage the controller Signal Transition Graph to extract and classify their …
Cost-effective and flexible asynchronous interconnect technology for GALS systems
D Bertozzi, G Miorandi, A Ghiribaldi, W Burleson… - IEEE Micro, 2020 - ieeexplore.ieee.org
In this article, a novel interconnect technology is presented for the cost-effective and flexible
design of asynchronous networks-on-chip. It delivers asynchrony in heterogeneous system …
design of asynchronous networks-on-chip. It delivers asynchrony in heterogeneous system …
Accurate assessment of bundled-data asynchronous NoCs enabled by a predictable and efficient hierarchical synthesis flow
Asynchronous interconnect technology leveraging transition signaling bundled-data is
gaining momentum as a promising solution for the chip-level connectivity of GALS (Globally …
gaining momentum as a promising solution for the chip-level connectivity of GALS (Globally …
A practical framework for specification, verification, and design of self-timed pipelines
J Simatic, A Cherkaoui, F Bertrand… - 2017 23rd IEEE …, 2017 - ieeexplore.ieee.org
Asynchronous circuits are interesting alternatives for implementing ultra-low power systems
but they are more challenging to design. This work provides methods for designers to …
but they are more challenging to design. This work provides methods for designers to …
Challenges in building an open-source flow from RTL to bundled-data design
Bundled-data designs can mitigate many of the ill effects of process, voltage, and
temperature (PVT) variations. This paper describes an open-source CAD flow to synthesize …
temperature (PVT) variations. This paper describes an open-source CAD flow to synthesize …