[HTML][HTML] Time-to-digital conversion techniques: A survey of recent developments
J Szyduczyński, D Kościelnik, M Miśkowicz - Measurement, 2023 - Elsevier
Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for
digital processing of analog signals encoded in time. Since design of time-mode circuits …
digital processing of analog signals encoded in time. Since design of time-mode circuits …
Recent developments and design challenges of high-performance ring oscillator CMOS time-to-digital converters
Time-to-digital converters (TDCs) are increasingly used as building blocks in biomedical
imaging, digital communication, and measurement instrumentation systems. When …
imaging, digital communication, and measurement instrumentation systems. When …
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- Integrated Jitter at 4.5-mW Power
This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-
time converter, placed in the feedback path, cancels out the quantization noise introduced …
time converter, placed in the feedback path, cancels out the quantization noise introduced …
A high-linearity, 17 ps precision time-to-digital converter based on a single-stage vernier delay loop fine interpolation
This paper presents a time-to-digital converter (TDC) architecture capable of reaching high-
precision and high-linearity with moderate area occupation per measurement channel. The …
precision and high-linearity with moderate area occupation per measurement channel. The …
A 3.7 mW low-noise wide-bandwidth 4.5 GHz digital fractional-N PLL using time amplifier-based TDC
A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider
to achieve low in-band noise with a wide bandwidth is presented. The fractional divider …
to achieve low in-band noise with a wide bandwidth is presented. The fractional divider …
A 3.6 mW, 90 nm CMOS gated-Vernier time-to-digital converter with an equivalent resolution of 3.2 ps
Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-
digital converter (TDC), where the already small quantization noise of the standard Vernier …
digital converter (TDC), where the already small quantization noise of the standard Vernier …
A low-power gateable Vernier ring oscillator time-to-digital converter for biomedical imaging applications
In this paper, a high resolution, high precision and ultra-low power consumption time-to-
digital converter (TDC) is presented. The proposed TDC is based on the gateable Vernier …
digital converter (TDC) is presented. The proposed TDC is based on the gateable Vernier …
A 2.2 GHz-242 dB-FOM 4.2 mW ADC-PLL using digital sub-sampling architecture
T Siriburanon, S Kondo, K Kimura… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain
digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional …
digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional …
A 1.25 ps Resolution 8b Cyclic TDC in 0.13 m CMOS
This paper describes the first implementation of the well-known cyclic ADC architecture into
a time-to-digital converter. With an asynchronous clocking scheme, an all-digital 1.5 b time …
a time-to-digital converter. With an asynchronous clocking scheme, an all-digital 1.5 b time …
A 10-bit 80-MS/s decision-select successive approximation TDC in 65-nm CMOS
This paper presents a 10-bit 80-MS/s successive approximation time-to-digital converter
(TDC) with a decision-select structure for on-chip timing measurement applications. Time …
(TDC) with a decision-select structure for on-chip timing measurement applications. Time …