A 10 nm FinFET 128 Mb SRAM with assist adjustment system for power, performance, and area optimization
Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040
6T SRAM bitcell is designed for high density (HD), and 0.049 for high performance (HP). The …
6T SRAM bitcell is designed for high density (HD), and 0.049 for high performance (HP). The …
A framework for monitoring microservice-oriented cloud applications in heterogeneous virtualization environments
Microservices have emerged as a new approach for developing and deploying cloud
applications that require higher levels of agility, scale, and reliability. To this end, a …
applications that require higher levels of agility, scale, and reliability. To this end, a …
LDAX A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis
M Awais, H Ghasemzadeh Mohammadi… - Proceedings of the 2021 …, 2021 - dl.acm.org
The majority of existing frameworks for automated synthesis of Approximate Circuits (AxCs)
employ a search-based Design Space Exploration (DSE) approach. This includes an …
employ a search-based Design Space Exploration (DSE) approach. This includes an …
A Statistical Cell Delay Model for Estimating the 3σ Delay by Matching Kurtosis
Accurate standard cell modeling is significant for circuit timing analysis and yield estimation.
With voltage decreasing to near-threshold, cell delay distribution becomes asymmetrical and …
With voltage decreasing to near-threshold, cell delay distribution becomes asymmetrical and …
Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation
Post-silicon validation is one of the most critical processes in modern semiconductor
manufacturing. Specifically, correct and deep understanding in test cases of manufactured …
manufacturing. Specifically, correct and deep understanding in test cases of manufactured …
Co-Simulating Region-Based Dynamic Voltage Scaling for FPGA Architecture Design
J Pfau, J Hernandez, M Reuter… - 2023 IEEE Nordic …, 2023 - ieeexplore.ieee.org
With rising importance of low power technology, researchers explore FPGA power
management ranging from static leakage reduction to Dynamic Voltage Scaling (DVS). VPR …
management ranging from static leakage reduction to Dynamic Voltage Scaling (DVS). VPR …
[PDF][PDF] Frameworks and methodologies for search-based approximate logic synthesis.
L Witschen - 2022 - digital.ub.uni-paderborn.de
Approximate computing has emerged as one way to meet the challenge of improving a
computing system's performance by trading off an application's quality against a target …
computing system's performance by trading off an application's quality against a target …
Power reduction and bti mitigation of data-cache memory based on the storage management of narrow-width values
N Rohbani, H Gau, S Mohammadinejad… - … Transactions on Very …, 2019 - ieeexplore.ieee.org
Power dissipation of on-chip cache memories contributes a large portion of a processor's
power consumption. Therefore, power management of cache memories is crucial in modern …
power consumption. Therefore, power management of cache memories is crucial in modern …
RFET Reconfigurable Devices: Power Aware FPGA Architectures and Toolflow
J Pfau - 2024 - publikationen.bibliothek.kit.edu
Der Leistungsaufnahme in modernen integrierter Schaltungen wird immer größere
Bedeutung beigemessen. Field Programmable Gate Arrays (FPGAs) sind durch ihren hohen …
Bedeutung beigemessen. Field Programmable Gate Arrays (FPGAs) sind durch ihren hohen …
SRAM Designing with Comparative Analysis using Planer and Non-Planer Nanodevice
The scaling of planer devices is a significant concern for the electronics industry. As the
device execution for the performance is estimated with drive current, this mainly depends on …
device execution for the performance is estimated with drive current, this mainly depends on …