Power will be the key limiter to system scalability as interconnection networks take up an
increasingly significant portion of system power. In this paper, we propose an architectural …

Leakage power is emerging as a key design challenge in current and future CMOS designs.
Since leakage is critically dependent on operating temperature and power supply, we …

Power has become a critical issue for field-programmable gate array (FPGA) vendors.
Understanding the power dissipation within FPGAs is the first step in developing power …

Because of the continued scaling of technology and supply-threshold voltage, leakage
power has become more significant in power dissipation of nanoscale CMOS circuits …

Purpose–Delay and power dissipation are the two major design constraints in very large
scale integration (VLSI) circuits. These arise due to millions of active devices and …

Converting a conventional contract into an electronic equivalent that can be executed and
enforced by computers is a challenging task. The difficulties are caused by the ambiguities …

This paper proposes an optimum methodology for assigning supply and threshold voltages
to modules in a CMOS circuit such that the overall energy consumption is minimized for a …

As silicon CMOS technology is scaled into the nanometer regime, the paradigm shift of
computer-aided design (CAD) technology is indispensable to cope with two major …

There is a growing need for accurate power models at the system level. Memory structures
such as caches, Branch Target Buffers (BTBs), and register files occupy significant area in …

We propose SyfriPow, a method for estimating the vectorless average power consumption of
gate-level circuits using sparse symbolic matrix inference. SyfriPow employs a probability …