Variation tolerant differential 8T SRAM cell for ultralow power applications
Low power and noise tolerant static random access memory (SRAM) cells are in high
demand today. This paper presents a stable differential SRAM cell that consumes low …
demand today. This paper presents a stable differential SRAM cell that consumes low …
Ultralow-voltage, minimum-energy CMOS
S Hanson, B Zhai, K Bernstein… - IBM journal of …, 2006 - ieeexplore.ieee.org
Energy efficiency has become a ubiquitous design requirement for digital circuits.
Aggressive supply-voltage scaling has emerged as the most effective way to reduce energy …
Aggressive supply-voltage scaling has emerged as the most effective way to reduce energy …
Leakage characterization of 10T SRAM cell
This paper presents a technique for designing a low-power and variability-aware SRAM cell.
The cell achieves low power dissipation due to its series-connected tail transistor and read …
The cell achieves low power dissipation due to its series-connected tail transistor and read …
Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow‐Power Applications
R Vaddi, S Dasgupta, RP Agarwal - VLSI Design, 2009 - Wiley Online Library
In recent years, subthreshold operation has gained a lot of attention due to ultra low‐power
consumption in applications requiring low to medium performance. It has also been shown …
consumption in applications requiring low to medium performance. It has also been shown …
Load balancing a cluster of web servers: using distributed packet rewriting
L Aversa, A Bestavros - Conference Proceedings of the 2000 …, 2000 - ieeexplore.ieee.org
We present and evaluate an implementation of a prototype scalable web server consisting of
a load-balanced cluster of hosts that collectively accept and service TCP connections. The …
a load-balanced cluster of hosts that collectively accept and service TCP connections. The …
Utilizing reverse short channel effect for optimal subthreshold circuit design
The impact of the Reverse Short Channel Effect (RSCE) on device current is stronger in the
subthreshold region due to the reduced Drain-Induced-Barrier-Lowering (DIBL) and the …
subthreshold region due to the reduced Drain-Induced-Barrier-Lowering (DIBL) and the …
Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS
R Vaddi, S Dasgupta… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
Digital circuits operating in a subthreshold region have gained wide interest due to their
suitability for applications requiring ultralow power consumption with low-to-medium …
suitability for applications requiring ultralow power consumption with low-to-medium …
A new frontier in ultralow power wireless links: Network-on-chip and chip-to-chip interconnects
This paper explores the general framework and prospects for on-chip and off-chip wireless
interconnects implemented for high-performance computing (HPC) systems in the context of …
interconnects implemented for high-performance computing (HPC) systems in the context of …
Nanometer device scaling in subthreshold logic and SRAM
S Hanson, M Seok, D Sylvester… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
Subthreshold circuit design is promising for future ultralow-energy sensor applications as
well as highly parallel high-performance processing. Device scaling has the potential to …
well as highly parallel high-performance processing. Device scaling has the potential to …
Heterogate junctionless tunnel field-effect transistor: future of low-power devices
Gate dielectric materials play a key role in device development and study for various
applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials …
applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials …