[图书][B] VLSI test principles and architectures: design for testability

LT Wang, CW Wu, X Wen - 2006 - books.google.com
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …

Deepgate2: Functionality-aware circuit representation learning

Z Shi, H Pan, S Khan, M Li, Y Liu… - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
Circuit representation learning aims to obtain neural repre-sentations of circuit elements and
has emerged as a promising research direction that can be applied to various EDA and logic …

Constraint extraction for pseudo-functional scan-based delay testing

YC Lin, F Lu, K Yang, KT Cheng - Proceedings of the 2005 Asia and …, 2005 - dl.acm.org
Recent research results have shown that the traditional structural testing for delay and
crosstalk faults may result in over-testing due to the non-trivial number of such faults that are …

A novel scheme to reduce power supply noise for high-quality at-speed scan testing

X Wen, K Miyase, S Kajihara, T Suzuki… - 2007 IEEE …, 2007 - ieeexplore.ieee.org
High-quality at-speed scan testing, characterized by high small-delay-defect detecting
capability, is indispensable to achieve high delay test quality for DSM circuits. However …

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

B Becker, R Drechsler, S Eggersglüß… - 2014 9th IEEE …, 2014 - ieeexplore.ieee.org
It is well-known that in principle automatic test pattern generation (ATPG) can be solved by
transforming the circuit and the fault considered into a Boolean satisfiability (SAT) instance …

Satformer: Transformer-based unsat core learning

Z Shi, M Li, Y Liu, S Khan, J Huang… - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
This paper introduces SATformer, a novel Transformer-based approach for the Boolean
Satisfiability (SAT) problem. Rather than solving the problem directly, SATformer …

[图书][B] Test pattern generation using Boolean proof engines

R Drechsler, S Eggersglüß, G Fey, D Tille - 2009 - books.google.com
In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG.
The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a …

Access time minimization in IEEE 1687 networks

R Krenz-Baath, FG Zadegan… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
IEEE 1687 enables flexible access to the embedded (on-chip) instruments that are needed
for post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board …

Evaluation of the statistical delay quality model

Y Sato, S Hamada, T Maeda, A Takatori… - Proceedings of the 2005 …, 2005 - dl.acm.org
In this paper we introduce a quality model that reflects fabrication process quality, design
delay margin, and test timing accuracy. The model provides a measure that can predict the …

PHAETON: A SAT-based framework for timing-aware path sensitization

M Sauer, B Becker, I Polian - IEEE Transactions on Computers, 2015 - ieeexplore.ieee.org
Knowledge about sensitizable paths through combinational logic is essential for numerous
design tasks. We present the framework PHAETON which identifies sensitizable paths and …