Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection
framework in Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and …

Network-on-Chip (NoC) is an efficient and scalable on-chip interconnection framework,
designed to address communication challenges in multiprocessor system-on-chips …

A three-dimensional Network-on-Chip (3D NoC) equips modern multicore processors with
good scalability, a small area, and high performance using vertical through-silicon vias …

This paper proposes a fault-tolerant mechanism including a reliable three-dimensional (3D)
topology structure named 3D DCMesh (3D duel-core connected mesh) and a fault-tolerant …

Because most of the algorithms presented are based on the well-known algorithms that are
studied and evaluated in this research. Finally, according to the results produced under …

The ever-shrinking size of a transistor has made Network on Chip (NoC) susceptible to
faults. A single error in the NoC can disrupt the entire communication. In this paper, we …

This paper proposes a simple and effective evaluation method for fault-tolerant routing
methods developed for Network-on-Chip (NoC)-based many-core processors. To cope with …

In order to guarantee the communication quality of large-scale multicore processors, 3D
Network-on-Chip has become the dominate component for interconnecting various IPs via …

Due to the faults in system fabrication and run time, designing an efficient fault-tolerant
routing algorithm with the property of deadlock-freeness is crucial for realizing dependable …

This paper proposes an extended two‐dimensional mesh Network‐on‐Chip architecture for
region‐based fault tolerant routing methods. The proposed architecture has an additional …