Scalable memory protection in the {PENGLAI} enclave
Secure hardware enclaves have been widely used for protecting security-critical
applications in the cloud. However, existing enclave designs fail to meet the requirements of …
applications in the cloud. However, existing enclave designs fail to meet the requirements of …
A survey of the RISC-V architecture software support
RISC-V is a novel open instruction set architecture that supports multiple platforms while
maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has …
maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has …
Securecells: A secure compartmentalized architecture
A Bhattacharyya, F Hofhammer, Y Li… - … IEEE Symposium on …, 2023 - ieeexplore.ieee.org
Modern programs are monolithic, combining code of varied provenance without isolation, all
the while running on network-connected devices. A vulnerability in any component may …
the while running on network-connected devices. A vulnerability in any component may …
Microkernel Goes General: Performance and Compatibility in the {HongMeng} Production Microkernel
The virtues of security, reliability, and extensibility have made state-of-the-art microkernels
prevalent in embedded and safety-critical scenarios. However, they face performance and …
prevalent in embedded and safety-critical scenarios. However, they face performance and …
Harmonizing performance and isolation in microkernels with efficient intra-kernel isolation and communication
This paper presents UnderBridge, a redesign of traditional microkernel OSes to harmonize
the tension between messaging performance and isolation. UnderBridge moves the OS …
the tension between messaging performance and isolation. UnderBridge moves the OS …
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources
Address translation is a performance bottleneck in data-intensive workloads due to large
datasets and irregular access patterns that lead to frequent high-latency page table walks …
datasets and irregular access patterns that lead to frequent high-latency page table walks …
A case against (most) context switches
JT Humphries, K Kaffes, D Mazières… - Proceedings of the …, 2021 - dl.acm.org
Multiplexing software threads onto hardware threads and serving interrupts, VM-exits, and
system calls require frequent context switches, causing high overheads and significant …
system calls require frequent context switches, causing high overheads and significant …
Userspace Bypass: Accelerating Syscall-intensive Applications
Context switching between kernel mode and user mode often causes prominent overhead,
which slows down applications with frequent system calls (or syscalls), eg, those with high …
which slows down applications with frequent system calls (or syscalls), eg, those with high …
Limitations and Opportunities of Modern Hardware Isolation Mechanisms
A surge in the number, complexity, and automation of targeted security attacks has triggered
a wave of interest in hardware support for isolation. Intel memory protection keys (MPK) …
a wave of interest in hardware support for isolation. Intel memory protection keys (MPK) …
The HitchHiker's Guide to High-Assurance System Observability Protection with Efficient Permission Switches
Protecting system observability records (logs) from compromised OSs has gained significant
traction in recent times, with several note-worthy approaches proposed. Unfortunately, none …
traction in recent times, with several note-worthy approaches proposed. Unfortunately, none …