Power delivery for 3D chip stacks: Physical modeling and design implication
Three-dimensional (3D) integration creates vast opportunities to improve performance and
the level of integration in nanoelectronic systems. However, 3D integration presents many …
the level of integration in nanoelectronic systems. However, 3D integration presents many …
MAPG: Memory access power gating
In mobile systems, the problems of short battery life and increased temperature are
exacerbated by wasted leakage power. Leakage power waste can be reduced by power …
exacerbated by wasted leakage power. Leakage power waste can be reduced by power …
3D fabrication options for high-performance CMOS technology
The last several decades have seen an incredible increase in the functionality of
computational systems. At its core, this capability has been driven by the scaling of …
computational systems. At its core, this capability has been driven by the scaling of …
Cu wafer bonding for 3D IC applications
This chapter describes a fabrication method for three-dimensional (3D) integrated circuits
(ICs) initially proposed and developed at the Microsystems Technology Laboratories (MTL) …
(ICs) initially proposed and developed at the Microsystems Technology Laboratories (MTL) …
Thermal and Power Delivery Aware Floorplanning for Heterogeneous Multi Core Design
Y Im, YS Cho, J Hwang, H Lee, J Yoo… - 2020 IEEE 70th …, 2020 - ieeexplore.ieee.org
Heat removal and power integrity have become major concerns in floor-planning of
heterogeneous multi core in system on a chip (SOC). Heterogeneous multi core brings new …
heterogeneous multi core in system on a chip (SOC). Heterogeneous multi core brings new …
Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI)
For the first time, compact physical models are derived in this work that enable quick
package-and chip-scale calculations of the power supply noise and incorporate the …
package-and chip-scale calculations of the power supply noise and incorporate the …
Supply noise and impedance of on-chip power distribution networks in ICs with nonuniform power consumption and interblock decoupling capacitors
J Rius - IEEE Transactions on Very Large Scale Integration …, 2014 - ieeexplore.ieee.org
An RLC model for on-chip power distribution networks (PDN) is presented for array and wire-
bonded integrated circuits including interblock decoupling capacitors and C4 impedances …
bonded integrated circuits including interblock decoupling capacitors and C4 impedances …
[图书][B] Compact physical models for power supply noise and chip/package co-design in gigascale integration (GSI) and three-dimensional integration systems
G Huang - 2008 - search.proquest.com
The objective of this dissertation is to derive a set of compact physical models addressing
power integrity issues in high performance gigascale integration (GSI) systems and three …
power integrity issues in high performance gigascale integration (GSI) systems and three …
A virtual channel calculation algorithm for application specific on-chip networks
LW Wang - 2010 Third International Conference on Intelligent …, 2010 - ieeexplore.ieee.org
A virtual channel (VC) calculation algorithm for wormhole-switched on-chip networks is
proposed. Traditionally, the virtual channels were allocated uniformly, which results in a …
proposed. Traditionally, the virtual channels were allocated uniformly, which results in a …
[图书][B] Low-latency techniques for improving system energy efficiency
RD Strong - 2013 - search.proquest.com
US data center energy consumption is expected to rise past 100 billion kWh in 2013.
Approximately 50% of this energy usage can be attributed to servers, networks, and storage …
Approximately 50% of this energy usage can be attributed to servers, networks, and storage …