[PDF][PDF] Area, delay and power comparison of adder topologies

R Uma, V Vijayan, M Mohanapriya… - International Journal of …, 2012 - academia.edu
Adders form an almost obligatory component of every contemporary integrated circuit. The
prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power …

[PDF][PDF] Design and analysis of low power compressors

S Karthick, S Karthika, S Valannathy - International Journal of …, 2012 - academia.edu
The power management has become a great concern due to the increased usage of
multimedia devices. Multipliers are the main sources of power consumption in these …

[PDF][PDF] In-Depth Survey on XOR Gate Design

M Babu, SK GA - IN-DEPTH, 2020 - researchgate.net
XOR gate has a very important role in most of the cryptographic algorithms. Because of
anticoincident property, the XOR gate can be used as a Cipher and the same architecture …

Digital signature technique with quantum‐dot cellular automata

A Kundu, B Debnath, J Chandra Das… - IET Quantum …, 2022 - Wiley Online Library
Quantum‐dot cellular automaton (QCA) is efficient nanotechnology that may be used as an
alternative to Complementary Metal Oxide Semiconductor technology. Here, computation …

Design and Execution of Enhanced Carry Increment Adder using Han-Carlson and Kogge-Stone adder Technique: Han-Carlson and Kogge-Stone adder is used to …

N Varshney, G Arya - 2019 3rd International conference on …, 2019 - ieeexplore.ieee.org
A complex digital circuit has adder as a basic unit. Overall circuit performance will depend
on the design of the basic adder circuit. So, if we reduce the delay of the basic adder unit …

Design and Implementation of an improved carry increment adder

AB Devi, M Kumar, R Laishram - arXiv preprint arXiv:1603.04094, 2016 - arxiv.org
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit
depends on the design of this basic adder unit. The speed of operation of a circuit is one of …

An efficient 5‐input exclusive‐OR circuit based on carbon nanotube FETs

R Zarhoun, MH Moaiyeri, SS Farahani, K Navi - ETRI Journal, 2014 - Wiley Online Library
The integration of digital circuits has a tight relation with the scaling down of silicon
technology. The continuous scaling down of the feature size of CMOS devices enters the …

[PDF][PDF] A comparative analysis of different 32-bit adder topologies with multiplexer based full adder

D Mohanapriya, DN Saravanakumar, E BIT - Int J Eng Sci, 2016 - academia.edu
Adders form an almost imperative component of every contemporary integrated circuit. Due
to the rapidly growing mobile industry not only the speed arithmetic unit but also less area …

Design and implementation of single electron transistor N-BIT multiplier

V Raut, PK Dakhole - 2014 International Conference on …, 2014 - ieeexplore.ieee.org
The ancient method of multiplication with low power device ie Single electron transistor is
used for designing is presented in this paper. SET which is low power device is used to …

Design of a low power, high speed and energy efficient 3 transistor XOR gate in 45nm technology using the conception of MVT methodology

K Dhar - 2014 International Conference on Control …, 2014 - ieeexplore.ieee.org
This paper puts forward the design of a low power, high speed and energy efficient XOR
gate comprising only 3 transistors in 45nm technology using the conception of Mixed …