[图书][B] Why systolic architecture?
HT Kung - 1982 - eecs.harvard.edu
Roughly, the cycle for developing a special-purpose system can be divided into three
phases–task definition, design, and implementation. During task definition, some system …
phases–task definition, design, and implementation. During task definition, some system …
[图书][B] Models of computation
JE Savage - 1998 - dna.caltech.edu
Models of Computation.ppt [Read-Only] Page 1 Models of Computation John E Savage
Computer Science Brown University CBSSS 2004 July 16, 2004 Page 2 CBSSS: JE Savage …
Computer Science Brown University CBSSS 2004 July 16, 2004 Page 2 CBSSS: JE Savage …
[PDF][PDF] Gemmini: An agile systolic array generator enabling systematic evaluations of deep-learning architectures
Advances in deep learning and neural networks have resulted in rapid development of
hardware accelerators that support them. A large majority of ASIC accelerators, however …
hardware accelerators that support them. A large majority of ASIC accelerators, however …
A generator of numerically-tailored and high-throughput accelerators for batched GEMMs
We propose a hardware generator of GEMM accelerators. Our generator produces vendor-
agnostic HDL describing highly customizable systolic arrays guided by accuracy and energy …
agnostic HDL describing highly customizable systolic arrays guided by accuracy and energy …
Parallelism in computer vision: A review
V Chaudhary, JK Aggarwal - Parallel algorithms for machine intelligence …, 1990 - Springer
Computer vision tasks require an enormous amount of computation, especially when the
data is in image form, demanding high-performance computers for practical, real-time …
data is in image form, demanding high-performance computers for practical, real-time …
Parallel computer architectures for image processing
AP Reeves - Computer Vision, Graphics, and Image Processing, 1984 - Elsevier
Image processing problems frequently involve large structured arrays of data and a need for
very rapid computation. Special parallel processing schemes have evolved over the last 20 …
very rapid computation. Special parallel processing schemes have evolved over the last 20 …
Two-level pipelined systolic array for multidimensional convolution
HT Kung, LM Ruane, DWL Yen - Image and Vision Computing, 1983 - Elsevier
This paper describes a systolic array for the computation of n-dimensional (nD) convolutions
for any positive integer n. Systolic systems usually achieve high performance by allowing …
for any positive integer n. Systolic systems usually achieve high performance by allowing …
Parallel 2-D convolution on a mesh connected array processor
SY Lee, JK Aggarwal - IEEE Transactions on Pattern Analysis …, 1987 - ieeexplore.ieee.org
In this correspondence, a parallel 2-D convolution scheme is presented. The processing
structure is a mesh connected array processor consisting of the same number of simple …
structure is a mesh connected array processor consisting of the same number of simple …
[图书][B] Multi-computer architectures for artificial intelligence: Toward fast, robust, parallel systems
L Uhr - 1987 - dl.acm.org
Multi-computer architectures for artificial intelligence: toward fast, robust, parallel systems |
Guide books skip to main content ACM Digital Library home ACM home Google, Inc. (search) …
Guide books skip to main content ACM Digital Library home ACM home Google, Inc. (search) …
Evolutionary Mapping Techniques for Systolic Computing System
C Bagavathi, O Saraniya - Deep Learning and Parallel Computing …, 2019 - Elsevier
Systolic arrays are hardware structures built for fast and efficient operation of regular
algorithms that perform the same task with different data at different time instants. Systolic …
algorithms that perform the same task with different data at different time instants. Systolic …