Reducing the drain leakage current in a double-gate junctionless mosfet using the electron screening effect
This study investigated the position of electrons and holes in the ON and OFF states of
double-gate junctionless transistors, and then three structures were proposed to create an …
double-gate junctionless transistors, and then three structures were proposed to create an …
Si3N4:HfO2 dual‐k spacer bulk planar junctionless transistor for mixed signal integrated circuits
R Garike, GC Patil - IET Circuits, Devices & Systems, 2019 - Wiley Online Library
For the first time halfnium oxide (HfO2) is being incorporated in the dual‐k spacers and has
been used in bulk planar junctionless transistor (BPJLT). It has been found that …
been used in bulk planar junctionless transistor (BPJLT). It has been found that …
Approach for fabricating JLT using chemically deposited cadmium sulphide and titanium dioxide
GC Patil, V Kristaparapu, ST Ingle… - Micro & Nano …, 2019 - Wiley Online Library
Cadmium sulphide and titanium dioxide‐based junctionless transistor (JLT) has been
demonstrated by using simple and low‐cost chemical bath deposition method. The …
demonstrated by using simple and low‐cost chemical bath deposition method. The …
Analog/RF performance of source-side only dual-k sidewall spacer trigate junctionless transistor with parametric variations
G Saini, S Choudhary - Superlattices and Microstructures, 2016 - Elsevier
In this paper, analog/RF performance of source side only dual-k spacer (Dual-kS) trigate
junctionless transistor (JLT) is investigated with respect to the parametric variations. It is …
junctionless transistor (JLT) is investigated with respect to the parametric variations. It is …
Buried Metal Silicon-on-Insulator Junctionless Transistor for Low Power CMOS Logic Circuits
KK Tiple, GC Patil - Silicon, 2023 - Springer
This paper deals with an innovative structure of silicon-on-insulator junctionless transistor
(SOIJLT) by incorporating a buried metal layer of proper work-function which creates the …
(SOIJLT) by incorporating a buried metal layer of proper work-function which creates the …
Negative capacitance δ ‐bulk planar junctionless transistor for low power applications
KB Bhagat, GC Patil - Micro & Nano Letters, 2019 - Wiley Online Library
The impact of substrate doping on the short‐channel effects (SCEs) of bulk‐planar
junctionless transistor (BPJLT) has been studied. It has been found that increasing substrate …
junctionless transistor (BPJLT) has been studied. It has been found that increasing substrate …
Dual-k HfO2 Spacer Bulk Planar Junctionless Transistor for Sub-30 nm Low Power CMOS
G Ramarao, IC Ghosekar… - 2017 14th IEEE India …, 2017 - ieeexplore.ieee.org
In this paper, we propose the use of dual-k spacers to improve the electrostatic integrity and
thereby scalability of bulk planar junctionless transistor (BPJLT). The proposed structure …
thereby scalability of bulk planar junctionless transistor (BPJLT). The proposed structure …