A survey of microarchitectural side-channel vulnerabilities, attacks, and defenses in cryptography

X Lou, T Zhang, J Jiang, Y Zhang - ACM Computing Surveys (CSUR), 2021 - dl.acm.org
Side-channel attacks have become a severe threat to the confidentiality of computer
applications and systems. One popular type of such attacks is the microarchitectural attack …

Adversarial interference and its mitigations in privacy-preserving collaborative machine learning

D Usynin, A Ziller, M Makowski, R Braren… - Nature Machine …, 2021 - nature.com
Despite the rapid increase of data available to train machine-learning algorithms in many
domains, several applications suffer from a paucity of representative and diverse data. The …

When the curious abandon honesty: Federated learning is not private

F Boenisch, A Dziedzic, R Schuster… - 2023 IEEE 8th …, 2023 - ieeexplore.ieee.org
In federated learning (FL), data does not leave personal devices when they are jointly
training a machine learning model. Instead, these devices share gradients, parameters, or …

{CURE}: A security architecture with {CUstomizable} and resilient enclaves

R Bahmani, F Brasser, G Dessouky… - 30th USENIX Security …, 2021 - usenix.org
Security architectures providing Trusted Execution Environments (TEEs) have been an
appealing research subject for a wide range of computer systems, from low-end embedded …

Prime+ Scope: Overcoming the observer effect for high-precision cache contention attacks

A Purnal, F Turan, I Verbauwhede - Proceedings of the 2021 ACM …, 2021 - dl.acm.org
Modern processors expose software to information leakage through shared
microarchitectural state. One of the most severe leakage channels is cache contention …

{MIRAGE}: Mitigating {Conflict-Based} Cache Attacks with a Practical {Fully-Associative} Design

G Saileshwar, M Qureshi - 30th USENIX Security Symposium (USENIX …, 2021 - usenix.org
Shared caches in processors are vulnerable to conflict-based side-channel attacks, whereby
an attacker can monitor the access pattern of a victim by evicting victim cache lines using …

Systematic analysis of randomization-based protected cache architectures

A Purnal, L Giner, D Gruss… - 2021 IEEE Symposium …, 2021 - ieeexplore.ieee.org
Recent secure cache designs aim to mitigate side-channel attacks by randomizing the
mapping from memory addresses to cache sets. As vendors investigate deployment of these …

{NVLeak}:{Off-Chip}{Side-Channel} Attacks via {Non-Volatile} Memory Systems

Z Wang, M Taram, D Moghimi, S Swanson… - 32nd USENIX Security …, 2023 - usenix.org
We study microarchitectural side-channel attacks and defenses on non-volatile RAM
(NVRAM) DIMMs. In this study, we first perform reverse-engineering of NVRAMs as …

{Side-Channel} Attacks on Optane Persistent Memory

S Liu, S Kanniwadi, M Schwarzl, A Kogler… - 32nd USENIX Security …, 2023 - usenix.org
There is a constant evolution of technology for cloud environments, including the
development of new memory storage technology, such as persistent memory. The newly …

DR. SGX: Automated and adjustable side-channel protection for SGX using data location randomization

F Brasser, S Capkun, A Dmitrienko, T Frassetto… - Proceedings of the 35th …, 2019 - dl.acm.org
Recent research has demonstrated that Intel's SGX is vulnerable to software-based side-
channel attacks. In a common attack, the adversary monitors CPU caches to infer secret …