Post-silicon validation opportunities, challenges and recent advances

S Mitra, SA Seshia, N Nicolici - Proceedings of the 47th Design …, 2010 - dl.acm.org
Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after
manufacture. Due to sheer design complexity, it is nearly impossible to detect and fix all …

Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug

HF Ko, N Nicolici - … Transactions on Computer-Aided Design of …, 2009 - ieeexplore.ieee.org
To locate and correct design errors that escape pre-silicon verification, silicon debug has
become a necessary step in the implementation flow of digital integrated circuits. Embedded …

Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA)

SB Park, T Hong, S Mitra - IEEE Transactions on Computer …, 2009 - ieeexplore.ieee.org
Instruction Footprint Recording and Analysis (IFRA) overcomes challenges associated with
an expensive step in post-silicon validation of processors-pinpointing the bug location and …

IFRA: Instruction footprint recording and analysis for post-silicon bug localization in processors

SB Park, S Mitra - Proceedings of the 45th annual Design Automation …, 2008 - dl.acm.org
The objective of IFRA, Instruction Footprint Recording and Analysis, is to overcome the
challenges associated with a very expensive step in post-silicon validation of processors …

Low cost debug architecture using lossy compression for silicon debug

E Anis, N Nicolici - 2007 Design, Automation & Test in Europe …, 2007 - ieeexplore.ieee.org
The size of on-chip trace buffers used for at-speed silicon debug limits the observation
window in any debug session. Whenever the debug experiment can be repeated, we …

Distributed embedded logic analysis for post-silicon validation of SOCs

HF Ko, AB Kinsman, N Nicolici - 2008 IEEE International Test …, 2008 - ieeexplore.ieee.org
Post-silicon validation is used to identify design errors in silicon. Its main limitation is real-
time observability of the circuit's internal nodes. In this paper, we introduce a novel design …

Automated trace signals identification and state restoration for improving observability in post-silicon validation

HF Ko, N Nicolici - Proceedings of the conference on Design …, 2008 - dl.acm.org
Embedded logic analysis has emerged as a powerful technique for identifying functional
bugs during post-silicon validation, as it enables at-speed acquisition of data from the circuit …

RATS: Restoration-aware trace signal selection for post-silicon validation

K Basu, P Mishra - IEEE Transactions on Very Large Scale …, 2012 - ieeexplore.ieee.org
Post-silicon validation is one of the most important and expensive tasks in modern
integrated circuit design methodology. The primary problem governing post-silicon …

[图书][B] Backspace: Formal analysis for post-silicon debug

FM De Paula, M Gort, AJ Hu, SJE Wilton, J Yang - 2008 - ieeexplore.ieee.org
Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a
new design behaves incorrectly. This problem now consumes over half of the overall …

Efficient trace signal selection for post silicon validation and debug

K Basu, P Mishra - 2011 24th Internatioal Conference on VLSI …, 2011 - ieeexplore.ieee.org
Post-silicon validation is an essential part of modern integrated circuit design to capture
bugs and design errors that escape pre-silicon validation phase. A major problem governing …