Integration of Gate Divider Logic to improve the effectiveness of PLL using Ring VCO Topology
RB Chithra, MB Savadatti… - 2024 Asia Pacific …, 2024 - ieeexplore.ieee.org
This paper introduces a new approach to increase the efficiency, minimizing the power
consumption and delay of Phase-locked loops (PLLs) by choosing power gating method …
consumption and delay of Phase-locked loops (PLLs) by choosing power gating method …