A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz
bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital …

The fundamentals and state of the art in fractional-N phase-locked-loop (PLL)-based
frequency synthesis are reviewed. Particular emphasis is placed on delta-sigma fractional-N …

This paper presents phase-locked loop (PLL) reference-spur reduction design techniques
exploiting a sub-sampling phase detector (SSPD)(which is also referred to as a sampling …

The high phase noise of ring oscillators has generally discouraged their use in RF synthesis.
This paper introduces an integer-N synthesizer that employs a type-I loop to achieve a wide …

This paper demonstrates that spurious tones in the output of a fractional-N PLL can be
reduced by replacing the DeltaSigma modulator with a new type of digital quantizer and …

This paper presents the design of a digital PLL which uses a high-resolution time-to-digital
converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to …

A fast-settling adaptive calibration technique is presented that makes phase noise
cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies …

The increasingly demanding performance requirements of communications systems, as well
as problems posed by the continued scaling of silicon technology, present numerous …

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which
operates with almost no performance gap (176/198 fs RMS jitter) between the integer and …

This paper presents a modified structure for the first-order digital delta-sigma modulator
(DDSM) which yields the maximum sequence length (N) for all constant digital inputs and for …