Graphics processor units (GPUs) are designed to efficiently exploit thread level parallelism
(TLP), multiplexing execution of 1000s of concurrent threads on a relatively smaller set of …

Software transactional memory offers an appealing alternative to locks by improving
programmability, reliability, and scalability. However, existing STMs are impractical because …

Non-determinism has long been recognized as one of the key challenges which restrict
parallel programmer productivity by complicating several phases of application …

This paper presents TMProf, a transactional memory (TM) profiler, based on three
visualization principles. These principles are (i) the precise graphical representation of …

Language-level transactions are said to provide “atomicity,” implying that the order of
operations within a transaction should be invisible to concurrent transactions and thus that …

The availability of commercial hardware transactionalmemory (TM) systems has not yet
been met with a rise in the numberof large-scale programs that use memory transactions …

Hardware Transactional Memory (HTM) systems implement version management and
conflict detection in hardware to guarantee that each transaction is atomic and executes in …

Programming with atomic sections is a promising alternative to locks since it raises the
abstraction and removes deadlocks at the programmer level. However, implementations of …

Programs that use hardware transactional memory (HTM) demand sophisticated
performance analysis tools when they suffer from performance losses. We have developed …

Transactional memory (TM) is an attractive platform for parallel programs, and several
software transactional memory (STM) designs have been presented. We explore and …