This paper proposes a novel master slave (MS) flip‐flop design achieved by using only 18
transistors with a single‐phase clock and mixed topology. This design has lowest …

Clock gating (CG) is a widely used design method for reducing the dynamic power
consumption in digital circuits. Although it is a mature technique, theoretical work and tools …

Two novel low power and high‐speed pulse triggered flip‐flops were presented in this
paper. Short circuit current was controlled, and race condition between pull‐up and pull …

The effectiveness of multi-objective optimization methods, especially the methods based on
Swarm Intelligence, has led the researchers to utilize them significantly to solve complex …

Variable supply clustered voltage scaling (VS‐CVS) is an effective way to decrease power
consumption without compromising performance. One of the major challenges in VS‐CVS …

Dual supply voltage scheme provides very effective solution to cut down power consumption
in digital integrated circuits design, where level converting flip–flops (LCFF) are the key …

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented,
in which short circuit current is controlled. Switching activity is decreased to reduce the …

The effectiveness of multi-objective optimization methods, especially the methods based on
Swarm Intelligence, has led the researchers to utilize them significantly to solve complex …

کارآیی روش‌های بهینه‌سازی چندهدفه به‌خصوص روش‌های مبتنی ‌بر هوش جمعی سبب شده است
پژوهشگران به‌منظور حل مسائل پیچیدة مهندسی با اهداف چندگانة متناقض به‌صورت چشمگیری به …‎