Overview and outlook of through‐silicon via (TSV) and 3D integrations
JH Lau - Microelectronics International, 2011 - emerald.com
Purpose–The purpose of this paper is to focus on through‐silicon via (TSV), with a new
concept that every chip or interposer could have two surfaces with circuits. Emphasis is …
concept that every chip or interposer could have two surfaces with circuits. Emphasis is …
Evolution, challenge, and outlook of TSV, 3D IC integration and 3D silicon integration
JH Lau - … symposium on advanced packaging materials (APM), 2011 - ieeexplore.ieee.org
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They
are different and in general the TSV (through-silicon via) separates 3D IC packaging from …
are different and in general the TSV (through-silicon via) separates 3D IC packaging from …
TSV manufacturing yield and hidden costs for 3D IC integration
JH Lau - 2010 Proceedings 60th electronic components and …, 2010 - ieeexplore.ieee.org
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They
are different and in general, the TSV (through-silicon-via) separates the 3D IC packaging …
are different and in general, the TSV (through-silicon-via) separates the 3D IC packaging …
Effects of TSVs (through-silicon vias) on thermal performances of 3D IC integration system-in-package (SiP)
JH Lau, TG Yue - Microelectronics Reliability, 2012 - Elsevier
Thermal performances of 3D IC integration system-in-package (SiP) with TSV (through
silicon via) interposer/chip are investigated based on heat-transfer and CFD (computational …
silicon via) interposer/chip are investigated based on heat-transfer and CFD (computational …
Evolution and outlook of TSV and 3D IC/Si integration
JH Lau - 2010 12th Electronics Packaging Technology …, 2010 - ieeexplore.ieee.org
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They
are different and in general the TSV (through-silicon via) separates 3D IC packaging from …
are different and in general the TSV (through-silicon via) separates 3D IC packaging from …
TSV-based 3-D ICs: Design methods and tools
Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
Chip-last (RDL-first) fan-out panel-level packaging (FOPLP) for heterogeneous integration
JH Lau, CT Ko, CY Peng, KM Yang… - Journal of …, 2020 - meridian.allenpress.com
In this investigation, the chip-last, redistribution-layer (RDL)–first, fan-out panel-level
packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the …
packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the …
[图书][B] Labs on chip: Principles, design and technology
E Iannone - 2018 - taylorfrancis.com
Labs on Chip: Principles, Design and Technology provides a complete reference for the
complex field of labs on chip in biotechnology. Merging three main areas—fluid dynamics …
complex field of labs on chip in biotechnology. Merging three main areas—fluid dynamics …
Power comparison of 2D, 3D and 2.5 D interconnect solutions and power optimization of interposer interconnects
This paper compares the power efficiency of multiple 2D, 2.5 D and 3D interconnect
scenarios, specifically DDR3 with PCB, DDR3 with interposers, LPDDR2 (3) with POP, wide …
scenarios, specifically DDR3 with PCB, DDR3 with interposers, LPDDR2 (3) with POP, wide …
Critical issues of TSV and 3D IC integration
JH Lau - Journal of microelectronics and electronic …, 2010 - meridian.allenpress.com
Moore's law has been the most powerful driver for the development of the microelectronic
industry. This law is grounded in lithography scaling and integration (in 2D) of all functions …
industry. This law is grounded in lithography scaling and integration (in 2D) of all functions …