This paper proposes a novel FinFET based hybrid logic design for line decoders, which
comprises of transmission gate logic (TGL), modified gate diffusion input (MGDI) logic and …

Address decoders play a vital role in Static Random-Access Memory (SRAM) memory array
architecture to fetch the data in less span of time. As compared to other memory devices …

This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode
Logic (DML) design style to allow working in two modes of operation (ie, dynamic for high …

A mixed-logic design scheme utilizing pass-transistor logic (PTL) and dual-value logic (DVL)
in combination with static CMOS logic for decoders in SRAMs is proposed. By using of the …

Address decoders are an integral part of random access memories. They are typically
implemented using fast logic optimised for low latency. The latter, however, are difficult to …

This paper presents a modified energy-efficient Dual Mode Transmission Gate Diffusion
Input (DMTGDI) design and is termed as M-DMTGDI. A contention issue in dynamic mode …

Decoders are one of the significant peripheral components of static randomaccess memory
(SRAM). As the CMOS technology moves towards nano scale regime, the leakage power …

This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-
based comparator optimized to operate in the dynamic mode. The parallel-prefix …

Abstract An easily-extendable 12-transistor 2-4 line decoder core is presented for the
random-access memory interface such as translation lookaside buffer and the first level data …

This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode
Logic (DML) design style to allow working in two modes of operation (ie, dynamic for high …