In today's manycore processors, the energy loss of more than 20% may result from inherent
inefficiencies of conventional power delivery system (PDS) design. By stacking multiple …

In this paper, an ultra-low power fast-convergence CORDIC processor is proposed for power-
constrained applications. Existing fast-convergence CORDIC methods are reviewed …

As chips increase in complexity with ever increasing power consumption, pressure in
efficient power delivery mechanism such as multi-VDD, voltage stacked and DVS continues …

This paper describes the development of a 65nm standard cell library designed for building
highly energy-efficient digital circuits. In total 43 logic cells and 19 special cells for clock-tree …

This paper presents a resource efficient level shifter circuit, which is capable of converting
input voltages below subthreshold to above threshold voltages, making it suitable for ultra …

In this article, an energy efficient and low delay architecture for voltage level shifter with the
help of dual current mirror approach has been discussed. Voltage shifter is competent of …

In recent years, due to the use of data warehouses, the subject of materialized view
maintanance is important. For quick access to data, data warehouses collect the necessary …

In this article, a power‐efficient hybrid voltage up level shifter (LS) is designed. By using a
combination of a current mirror (CM) and a cross‐coupled pMOS pair in a pull‐up circuitry …

Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a
direct square proportion of supply voltage on dynamic power. If the supply voltage is high …

This study examines two different forms of energy-saving and rapid voltage level changers
are designed in this research. This article provides comprehensive information on logic …