Aspects of this disclosure relate to detecting and recording information associated with
electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For …

Disclosed is a protection circuit capable of avoiding break down of a gate insulating film of a
MOSFET and having an appropriate Snap-back Voltage in terms of reliability. In order to …

The systems, methods, and devices of the invention each have several aspects, no single
one of which is solely respon sible for its desirable attributes. Without limiting the scope of …

Electrostatic Discharge (ESD) protection is a critical prob lem for modern integrated circuits.
With a low breakdown Voltage of transistors in Submicron processes, it is important to …

Thus, a need has arisen for an electrostatic discharge protection circuit with a trigger-Switch
that addresses the disadvantages and deficiencies of the prior art. In particular, a need has …

Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a
circuit that is electrically con nected to first and second circuit nodes from an ESD event. The …

In an embodiment, an electrical over-stress (EOS) circuit includes a detection circuit coupled
between first and second Supply terminals and configured to detect a perturbation in a …

US7385793B1 - Cascode active shunt gate oxide project during electrostatic discharge event -
Google Patents US7385793B1 - Cascode active shunt gate oxide project during electrostatic …

The disclosed technology generally relates to integrated circuit devices with wear out
monitoring capability. An integrated circuit device includes a wear-out monitor device …

An ESD clamp circuit for use between separate power rails. An ESD clamp is based on a
wide nMOSFET. A symmetrical circuit is designed vis-a-vis the two power rails, with respect …