Analog/RF Performance Projection of Ultra-Steep Si Doped HfO2 Based Negative Capacitance Electrostatically Doped TFET: A Process Variation Resistant Design
The incorporation of Si doped Hf O 2 in negative capacitance electrostatically doped TFET
realizes ultra-steep and process variation resistant structure. Here, Si: Hf O 2 is the gate …
realizes ultra-steep and process variation resistant structure. Here, Si: Hf O 2 is the gate …
Trench IGBT with stepped doped collector for low energy loss
In this paper, a novel technique of variation doping profile in collector region for trench IGBT
is proposed. The collector region is segregated in three sections such that the section with …
is proposed. The collector region is segregated in three sections such that the section with …
Lateral variation-doped insulated gate bipolar transistor for low on-state voltage with low loss
In this letter, a new structure of Insulated Gate Bipolar Transistor (IGBT) with lateral variation
doping concept in epitaxial region is presented. In the drift region, the lateral variation …
doping concept in epitaxial region is presented. In the drift region, the lateral variation …
1.4 kv planar gate superjunction igbt with stepped doping profile in drift and collector region
N Gupta, A Naugarhiya - Silicon, 2021 - Springer
In this paper, stepped doping profile in alternate pillars and collector region of superjunction
IGBT structure is presented. The proposed device structure consists of lightly and heavily …
IGBT structure is presented. The proposed device structure consists of lightly and heavily …
Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications
In this paper, trench superjunction MOS (SJ UMOS) utilizing workfunction engineered
stepped gate for performance enhancement is proposed. N+ polysilicon (Φ m= 4.17 eV) …
stepped gate for performance enhancement is proposed. N+ polysilicon (Φ m= 4.17 eV) …
An assessment of step patterned gate oxide superjunction trench mosfet for potential benefits
A 600 V-class step patterned gate oxide trench (SPGOT) superjunction vertical device
incorporating gate engineering is proposed in this paper. An n^+ n+ polysilicon gate is …
incorporating gate engineering is proposed in this paper. An n^+ n+ polysilicon gate is …
Electrical characteristic investigation of variation vertical doping superjunction UMOS
P Nautiyal, A Agrawal, S Kumari, H Sahu… - 2019 IEEE 16th India …, 2019 - ieeexplore.ieee.org
Superjunction UMOS (SJ UMOS) with variation vertical doping in the drift region is
presented in this paper. The N-drift region of proposed structure is doped in a manner that …
presented in this paper. The N-drift region of proposed structure is doped in a manner that …
Performance evaluation of superjunction UMOS with dual polysilicon gate
P Nautiyal, A Naugarhiya, S Verma - Materials Today: Proceedings, 2021 - Elsevier
Abstract A modified Superjunction (SJ) UMOS employing dual polysilicon material that is P+
polysilicon and N+ polysilicon on lower and upper portion of gate respectively is proposed in …
polysilicon and N+ polysilicon on lower and upper portion of gate respectively is proposed in …
An improved SJ UMOS with modified gate electrode to reduce gate charge
PK Kushwaha, P Nautiyal, A Gupta… - 2019 9th Annual …, 2019 - ieeexplore.ieee.org
An improved superjunction (SJ) device structure with modified gate electrode has been
proposed in this paper. The trench gate has been altered to reduce gate capacitance …
proposed in this paper. The trench gate has been altered to reduce gate capacitance …
Gate Engineered Vertical Mosfet with Reduced Specific Resistance and Switching Delay
A Naugarhiyaa, S Singha, P Nautiyala… - ICT for Competitive …, 2020 - taylorfrancis.com
An enhanced device structure employing gate engineering on the planar gate power
VDMOS has been implemented here. The device GE VDMOS employs N+ and P+ …
VDMOS has been implemented here. The device GE VDMOS employs N+ and P+ …