Recent advances on HEVC inter-frame coding: From optimization to implementation and beyond

Y Zhang, C Zhang, R Fan, S Ma… - IEEE transactions on …, 2019 - ieeexplore.ieee.org
High Efficiency Video Coding (HEVC) has doubled the video compression ratio with
equivalent subjective quality as compared to its predecessor H. 264/AVC. The significant …

Power-efficient sum of absolute differences hardware architecture using adder compressors for integer motion estimation design

B Silveira, G Paim, B Abreu, M Grellert… - … on Circuits and …, 2017 - ieeexplore.ieee.org
Sum of absolute differences (SAD) calculation is one of the most time-consuming operations
of video encoders compatible with the high efficiency video coding standard. SAD hardware …

Optimisation of HEVC motion estimation exploiting SAD and SSD GPU‐based implementation

R Khemiri, H Kibeya, FE Sayadi, N Bahri… - IET Image …, 2018 - Wiley Online Library
The new High‐Efficiency Video Coding (HEVC) standard doubles the video compression
ratio compared to the previous H. 264/AVC at the same video quality and without any …

A highly parallel SAD architecture for motion estimation in HEVC encoder

A Medhat, A Shalaby, MS Sayed… - 2014 IEEE Asia …, 2014 - ieeexplore.ieee.org
The high computational cost of the motion estimation module in the new HEVC standard
raises the need for efficient hardware architectures that can meet the real-time processing …

High speed SAD architectures for variable block size motion estimation in HEVC video coding

P Nalluri, LN Alves, A Navarro - 2014 IEEE international …, 2014 - ieeexplore.ieee.org
HEVC is the latest video coding standard aimed to compress double to that of its
predecessor standard H. 264/AVC at the cost of increased coding complexity. Motion …

A reconfigurable hardware architecture for fractional pixel interpolation in high efficiency video coding

CM Diniz, M Shafique, S Bampi… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
We present a novel reconfigurable hardware architecture for interpolation filtering in high
efficient video coding that adapts to run-time changes of the number of interpolation filter …

On Combining Wavefront and Tile Parallelism with a Novel GPU-Friendly Fast Search

GI Papaioannou, M Koziri, T Loukopoulos… - Electronics, 2023 - mdpi.com
As the necessity of supporting ever-increasing demands in video resolution leads to new
video coding standards, the challenge of harnessing their computational overhead becomes …

Real-time motion estimation diamond search algorithm for the new high efficiency video coding on FPGA

R Khemiri, H Kibeya, H Loukil, FE Sayadi, M Atri… - … Integrated Circuits and …, 2018 - Springer
High efficiency video coding (HEVC) is the latest video coding standard aimed to replace the
H. 264/AVC standard according to its high coding performance, which allows it to be mostly …

Bi-predictive motion estimation for HEVC on a graphics processing unit (GPU)

S Radicke, JU Hahn, Q Wang… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
High Efficiency Video Coding (HEVC), the latest video compression standard, will play an
important role in many multimedia applications in the foreseeable future. Its superior …

Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding

G Paim, GM Santana, BA Abreu, LMG Rocha… - Journal of Real-Time …, 2020 - Springer
The sum of absolute difference (SAD) calculation is one of the most computing-intensive
operations in video encoders compatible with recent standards, such as high-efficiency …