Logical design flow with structural compatability verification

TS Kukal, N Gupta, S Durrill, V Khanna… - US Patent 8,732,651, 2014 - Google Patents
A design system provides data structures to store parameters of physical structures that can
be viewed and modified in a front-end process through a logical design interface. In this …

Method for estimating substrate noise in mixed signal integrated circuits

S Sinha, B Ghosh, RN Srinivasa, SN Kiel - US Patent 6,986,113, 2006 - Google Patents
(57) ABSTRACT A method for estimating noise in an integrated circuit Substrate. A model
file is created for a technology process for fabricating the integrated circuit. Noise generated …

Interconnect-aware integrated circuit design

D Goren, R Gordin, M Zelikson - US Patent 7,080,340, 2006 - Google Patents
In a system 10 for designing an integrated circuit, a preliminary design of the integrated
circuit is defined and critical interconnect lines in the preliminary design are identified …

Topology based wire shielding generation

TN Valine - US Patent 7,003,750, 2006 - Google Patents
Integrated circuits are typically composed of a multitude of circuit components and
interconnecting structures and are widely manufactured on semiconductor chips to process …

Method and system for schematic-visualization driven topologically-equivalent layout design in RFSiP

A Tripathi, A Jain, P Choudhary… - US Patent …, 2013 - Google Patents
An improved approach for automatically generating physical layout constraints and topology
that are visually in-sync with the logic schematic created for simulation is described. The …

Method and computer program for generating grounded shielding wires for signal wiring

A Nikitin, R Scepanovic, I Kucherenko, W Lau… - US Patent …, 2013 - Google Patents
The present application is a divisional of and claims prior ity from US patent application Ser.
No. 13/173,855, filed Jun. 30, 2011, which is a divisional of US patent application Ser. No …

Method and apparatus for model-order reduction and sensitivity analysis

HJ Lee, CC Chu, WS Feng - US Patent 7,216,309, 2007 - Google Patents
Computer time for modeling VLSI interconnection circuits is reduced by using symmetric
properties of modified nodal analysis formulation. The modeling uses modified nodal …

Semiconductor design layout pattern formation method and graphic pattern formation unit

M Yamagiwa, T Tanimoto, A Misaka… - US Patent App. 10 …, 2004 - Google Patents
Reduction in labor of the operations for evaluating the amount of retrogression of end
portions in a line pattern, and the Simplification of the CAD processing for a mask are …

System and method to improve chip yield, reliability and performance

HA Bonges III - US Patent 8,185,859, 2012 - Google Patents
In one aspect of the invention, machine-executable instruc tions embodied in a machine-
readable memory or storage device are used to build a network in a previously created …

Method and system for design and modeling of vertical interconnects for 3DI applications

R Gordin, D Goren - US Patent 8,448,119, 2013 - Google Patents
A system and method for design and modeling of vertical interconnects for 3DI applications.
A design and modeling methodology of vertical interconnects for 3DI applications includes …