Modern development methods and tools for embedded reconfigurable systems: A survey

L Jóźwiak, N Nedjah, M Figueroa - Integration, 2010 - Elsevier
Heterogeneous reconfigurable systems provide drastically higher performance and lower
power consumption than traditional CPU-centric systems. Moreover, they do it at much lower …

Reconfigurable computing architectures

R Tessier, K Pocek, A DeHon - Proceedings of the IEEE, 2015 - ieeexplore.ieee.org
Reconfigurable architectures can bring unique capabilities to computational tasks. They
offer the performance and energy efficiency of hardware with the flexibility of software. In …

[图书][B] Reconfigurable computing: the theory and practice of FPGA-based computation

S Hauck, A DeHon - 2010 - books.google.com
Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap
between the separate worlds of hardware and software design—the key feature of …

Design space exploration and implementation of a high performance and low area coarse grained reconfigurable processor

D Suh, K Kwon, S Kim, S Ryu… - … conference on field …, 2012 - ieeexplore.ieee.org
Coarse Grained Reconfigurable Architectures (CGRAs) have played a key role in the area of
domain specific processors due to their programmability and runtime reconfigurability. The …

Implementation of a coarse-grained reconfigurable media processor for AVC decoder

B Mei, B De Sutter, T Vander Aa, M Wouters… - Journal of signal …, 2008 - Springer
Abstract Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) is a
templatized coarse-grained reconfigurable processor architecture. It targets at embedded …

Adres & dresc: Architecture and compiler for coarse-grain reconfigurable processors

B Mei, M Berekovic, JY Mignolet - Fine-and coarse-grain reconfigurable …, 2007 - Springer
Nowadays, a typical embedded system requires high performance to perform tasks such as
video encoding/decoding at run-time. It should consume little energy to work hours or even …

System-level modeling of dynamically reconfigurable hardware with SystemC

A Pelkonen, K Masselos… - … International Parallel and …, 2003 - ieeexplore.ieee.org
To cope with the increasing demand for higher computational power and flexibility,
dynamically reconfigurable blocks have become an important part inside a system-on-chip …

Asynchronous algorithms in MapReduce

K Kambatla, N Rapolu, S Jagannathan… - … Conference on Cluster …, 2010 - ieeexplore.ieee.org
Asynchronous algorithms have been demonstrated to improve scalability of a variety of
applications in parallel environments. Their distributed adaptations have received relatively …

An optimal algorithm for minimizing run-time reconfiguration delay

S Ghiasi, A Nahapetian, M Sarrafzadeh - ACM Transactions on …, 2004 - dl.acm.org
Reconfiguration delay is one of the major barriers in the way of dynamically adapting a
system to its application requirements. The run-time reconfiguration delay is quite …

A design methodology for dynamic reconfiguration: The caronte architecture

F Ferrandi, MD Santambrogio… - 19th IEEE International …, 2005 - ieeexplore.ieee.org
The most common reconfigurable devices today are field programmable gate arrays,
FPGAs. Aim of this paper is to propose a design methodology for dynamically reconfigurable …