A survey of test and reliability solutions for magnetic random access memories
Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a
significant part of system power consumption. Though widely used, nonvolatile Flash …
significant part of system power consumption. Though widely used, nonvolatile Flash …
Data block manipulation for error rate reduction in STT-MRAM based main memory
Downscaling of semiconductor technology has led DRAM-based main memories to lag
behind emerging non-volatile memories, eg, Spin-Transfer Torque Magnetic Random …
behind emerging non-volatile memories, eg, Spin-Transfer Torque Magnetic Random …
3RSeT: Read disturbance rate reduction in STT-MRAM caches by selective tag comparison
E Cheshmikhani, H Farbeh… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Recent development in memory technologies has introduced Spin-Transfer Torque
Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip …
Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip …
A system-level framework for analytical and empirical reliability exploration of STT-MRAM caches
E Cheshmikhani, H Farbeh… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising
replacement for static random access memory (SRAM) technology in large last-level cache …
replacement for static random access memory (SRAM) technology in large last-level cache …
Mitigating negative impacts of read disturb in SSDs
Read disturb is a circuit-level noise in solid-state drives (SSDs), which may corrupt existing
data in SSD blocks and then cause high read error rate and longer read latency. The …
data in SSD blocks and then cause high read error rate and longer read latency. The …
ECC-United Cache: Maximizing efficiency of error detection/correction codes in associative cache memories
Error Detection/Correction Codes (EDCs/ECCs) are the most conventional approaches to
protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is …
protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is …
CRP: Conditional replacement policy for reliability enhancement of STT-MRAM caches
Driven by the trends of emerging technologies in on-chip memories, with increasing the size
of last-level caches (LLCs), spin-transfer torque magnetic random access memories (STT …
of last-level caches (LLCs), spin-transfer torque magnetic random access memories (STT …
CoPA: Cold page awakening to overcome retention failures in STT-MRAM based i/O buffers
M Hadizadeh, E Cheshmikhani… - … on Parallel and …, 2021 - ieeexplore.ieee.org
Performance and reliability are two prominent factors in the design of data storage systems.
To achieve higher performance, recently storage system designers use (DRAM)-based …
To achieve higher performance, recently storage system designers use (DRAM)-based …
Experimental and Theoretical Investigation of Intracell Magnetic Coupling-Induced Variability of Spin-Transfer Torque Magnetic RAMs
The impact of intracell magnetic coupling on spin transfer torque-magnetic random access
memory (STT-MRAM) device-to-device variability has been investigated based on …
memory (STT-MRAM) device-to-device variability has been investigated based on …
STAIR: High reliable STT-MRAM aware multi-level I/O cache architecture by adaptive ECC allocation
M Hadizadeh, E Cheshmikhani… - 2020 Design, Automation …, 2020 - ieeexplore.ieee.org
Hybrid Multi-Level Cache Architectures (HCAs) are promising solutions for the growing need
of high-performance and cost-efficient data storage systems. HCAs employ a high endurable …
of high-performance and cost-efficient data storage systems. HCAs employ a high endurable …