Highly pipelined asynchronous FPGAs
J Teifel, R Manohar - proceedings of the 2004 ACM/SIGDA 12th …, 2004 - dl.acm.org
We present the design of a high-performance, highly pipelined asynchronous FPGA. We
describe a very fine-grain pipelined logic block and routing interconnect architecture, and …
describe a very fine-grain pipelined logic block and routing interconnect architecture, and …
An asynchronous dataflow FPGA architecture
J Teifel, R Manohar - IEEE Transactions on Computers, 2004 - ieeexplore.ieee.org
We discuss the design of a high-performance field programmable gate array (FPGA)
architecture that efficiently prototypes asynchronous (clockless) logic. In this FPGA …
architecture that efficiently prototypes asynchronous (clockless) logic. In this FPGA …
Elastic circuits
J Carmona, J Cortadella… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
Elasticity in circuits and systems provides tolerance to variations in computation and
communication delays. This paper presents a comprehensive overview of elastic circuits for …
communication delays. This paper presents a comprehensive overview of elastic circuits for …
Data analysis and statistics: an expository overview
JW Tukey, MB Wilk - Proceedings of the November 7-10, 1966, fall joint …, 1966 - dl.acm.org
DATA ANALYSIS AND STATISTICS: AN EXPOSITORY OVERVIEW* Page 1 DATA ANALYSIS
AND STATISTICS: AN EXPOSITORY OVERVIEW* JW Tukey and MB Wilk Princeton University …
AND STATISTICS: AN EXPOSITORY OVERVIEW* JW Tukey and MB Wilk Princeton University …
Buffer placement and sizing for high-performance dataflow circuits
Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet,
effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits …
effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits …
RTL synthesis: From logic synthesis to automatic pipelining
J Cortadella, M Galceran-Oms… - Proceedings of the …, 2015 - ieeexplore.ieee.org
Design automation has been one of the main propellers of the semiconductor industry with
logic synthesis being one of the core technologies in this field. This article reviews the …
logic synthesis being one of the core technologies in this field. This article reviews the …
Formal analysis of MPI-based parallel programs
Formal analysis of MPI-based parallel programs Page 1 82 CommunICatIonS of tHe aCm |
DeceMBer 2011 | voL. 54 | No. 12 contributed articles MosT ParaLLeL CoMPUTiNG applications …
DeceMBer 2011 | voL. 54 | No. 12 contributed articles MosT ParaLLeL CoMPUTiNG applications …
Slack matching asynchronous designs
Slack matching is the problem of adding pipeline buffers to an asynchronous pipelined
design in order to prevent stalls and improve performance. This paper addresses the …
design in order to prevent stalls and improve performance. This paper addresses the …
Fault detection and isolation techniques for quasi delay-insensitive circuits
C LaFrieda, R Manohar - International Conference on …, 2004 - ieeexplore.ieee.org
This paper presents a circuit fault detection and isolation technique for quasi delay-
insensitive asynchronous circuits. We achieve fault isolation by a combination of physical …
insensitive asynchronous circuits. We achieve fault isolation by a combination of physical …
Synchronizability of communicating finite state machines is not decidable
A system of communicating finite state machines is synchronizable if its send trace
semantics, ie the set of sequences of sendings it can perform, is the same when its …
semantics, ie the set of sequences of sendings it can perform, is the same when its …