State of the art and future perspectives in advanced CMOS technology
The international technology roadmap of semiconductors (ITRS) is approaching the
historical end point and we observe that the semiconductor industry is driving …
historical end point and we observe that the semiconductor industry is driving …
Miniaturization of CMOS
HH Radamson, X He, Q Zhang, J Liu, H Cui, J Xiang… - Micromachines, 2019 - mdpi.com
When the international technology roadmap of semiconductors (ITRS) started almost five
decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) …
decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) …
New structure transistors for advanced technology node CMOS ICs
Q Zhang, Y Zhang, Y Luo, H Yin - National Science Review, 2024 - academic.oup.com
Over recent decades, advancements in complementary metal-oxide-semiconductor
integrated circuits (ICs) have mainly relied on structural innovations in transistors. From …
integrated circuits (ICs) have mainly relied on structural innovations in transistors. From …
Scaling challenges for advanced CMOS devices
The economic health of the semiconductor industry requires substantial scaling of chip
power, performance, and area with every new technology node that is ramped into …
power, performance, and area with every new technology node that is ramped into …
Optimization of structure and electrical characteristics for four-layer vertically-stacked horizontal gate-all-around Si nanosheets devices
Q Zhang, J Gu, R Xu, L Cao, J Li, Z Wu, G Wang, J Yao… - Nanomaterials, 2021 - mdpi.com
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si
nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release …
nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release …
Bottom oxide bulk FinFETs without punch-through-stopper for extending toward 5-nm node
Structural advancements of 5-nm node bulk fin-shaped field-effect transistors (FinFETs)
without punch-through-stopper (PTS) were introduced using fully calibrated TCAD for the …
without punch-through-stopper (PTS) were introduced using fully calibrated TCAD for the …
Channel engineering assisted performance enhancement of metal gate sub-10nm ballistic SiNWFET for futuristic device applications
The progress in silicon technology has brought us metal oxide semiconductor (MOS)
manufacturing technologies with physical gate length of about 14 nanometers and …
manufacturing technologies with physical gate length of about 14 nanometers and …
DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications
The device dimensions have been consistently scaling down since many developing
technologies need smaller and faster integrated circuits for advancement and improvement …
technologies need smaller and faster integrated circuits for advancement and improvement …
Influence of the hard masks profiles on formation of nanometer Si scalloped fins arrays
Q Zhang, H Tu, H Yin, F Wei, J Li, L Meng… - Microelectronic …, 2018 - Elsevier
In this work, the impact of hard masks (HMs) profiles on nanometer scalloped-fins (S-fins) by
reactive ion etching (RIE) is extensively investigated. A popular spacer image transfer (SIT) …
reactive ion etching (RIE) is extensively investigated. A popular spacer image transfer (SIT) …
Oxide isolated fin-type field-effect transistors
R Bao, H Jagannathan, PC Jamison… - US Patent 10,680,083, 2020 - Google Patents
According to an embodiment of the present invention, a semiconductor structure includes a
semiconductor substrate and a plurality of fins located on the semiconductor substrate. The …
semiconductor substrate and a plurality of fins located on the semiconductor substrate. The …