Phase coherent frequency hopping in direct digital synthesizers and phase locked loops
Phase coherent, frequency hopping direct digital synthesizer (DDS) and Type-II phase
locked loop (PLL) circuits are presented in this paper. The proposed approach eliminates …
locked loop (PLL) circuits are presented in this paper. The proposed approach eliminates …
System-on-a-chip clock phase management using fractional-N PLLs
J Zhuang, F Bossu - US Patent 10,116,315, 2018 - Google Patents
A clock distribution architecture is provided in which the output clock signals from a plurality
of fractional-N PLLs have a known phase relationship because each fractional-N PLL is …
of fractional-N PLLs have a known phase relationship because each fractional-N PLL is …
Access schemes for section-based data protection in a memory device
RE Fackenthal, D Vimercati, J Javanifard - US Patent 10,855,295, 2020 - Google Patents
Methods, systems, and devices for section-based data protection in a memory device are
described. In one example, a memory device may include a set memory sections each …
described. In one example, a memory device may include a set memory sections each …
Systems and methods for all-digital phase locked loop
J Van Den Heuvel, E Bechthum - US Patent 11,424,747, 2022 - Google Patents
An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern
generator adapted to generate a frequency control word (FCW) based on a predefined …
generator adapted to generate a frequency control word (FCW) based on a predefined …
Phase coherent frequency synthesis
Techniques are provided for phase coherent frequency syn thesis. An embodiment includes
a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to …
a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to …
DLL circuit having variable clock divider
Y Satoh - US Patent 10,931,289, 2021 - Google Patents
Disclosed herein is an apparatus that includes a variable clock divider configured to divide a
first clock signal to generate a second clock signal, a delay circuit configured to delay the …
first clock signal to generate a second clock signal, a delay circuit configured to delay the …
Phase lock loop (pll) synchronization
DF Jacquet, M Ghazali, M Kahrizi… - US Patent App. 18 …, 2023 - Google Patents
US20230378960A1 - Phase lock loop (pll) synchronization - Google Patents
US20230378960A1 - Phase lock loop (pll) synchronization - Google Patents Phase lock …
US20230378960A1 - Phase lock loop (pll) synchronization - Google Patents Phase lock …
Phase coherent frequency synthesis
Techniques are provided for phase coherent frequency synthesis. An embodiment includes
a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to …
a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to …
Multi modulus frequency divider and electronic device
Y Zhou - US Patent 11,411,570, 2022 - Google Patents
The present disclosure provides a multi modulus frequency divider and an electronic device.
The duty cycle adjusting circuit in the multi modulus frequency divider is configured to …
The duty cycle adjusting circuit in the multi modulus frequency divider is configured to …
Phase lock loop (PLL) synchronization
DF Jacquet, M Ghazali, M Kahrizi, A Tantos - US Patent 11,711,084, 2023 - Google Patents
In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to
receive a timing signal and a reference clock signal. The IC chips is configured to a …
receive a timing signal and a reference clock signal. The IC chips is configured to a …