Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs

CW Lin, MCT Chao, CC Hsu - 2013 IEEE 31st VLSI Test …, 2013 - ieeexplore.ieee.org
When CMOS technologies enter nanometer scale, FinFET has become one of the most
promising devices because of the superior electrical characteristics. Nonetheless, due to the …

Enhanced gate-induced floating-body effect in PD SOI MOSFET under external mechanical strain

CH Dai, TC Chang, AK Chu, YJ Kuo, SC Chen… - Surface and Coatings …, 2010 - Elsevier
The influence of tensile mechanical strain on gate-induced floating-body effect (GIFBE) in
advanced partially depleted SOI n-MOSFETs was investigated. Both drain current and …

Analog parameters of solid source Zn diffusion InXGa1− XAs nTFETs down to 10 K

C Bordallo, JA Martino, PGD Agopian… - Semiconductor …, 2016 - iopscience.iop.org
The analog parameters of In 0.53 Ga 0.47 As and In 0.7 Ga 0.3 As nTFETs with solid state
Zn diffused source are investigated from room temperature down to 10 K. The In 0.7 Ga 0.3 …

Gate Oxide Thickness Influence on the Gate Induced Floating Body Effect in SOI Technology

PGD Agopian, JA Martino, E Simoen… - Journal of Integrated …, 2008 - jics.org.br
In this work, we explore the gate oxide thickness influence on the Gate Induced Floating
Body effect (GIFBE). This study was performed through two-dimensional numerical …

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

PG Der Agopian, JA Martino, E Simoen, C Claeys - Solid-state electronics, 2008 - Elsevier
The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted
(FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results …

Etude des phénomènes de transport de porteurs et du bruit basse fréquence en fonction de la température dans les transistors MOSFETs nanométriques (FinFETs)

R Talmat - 2011 - hal.science
Au cours de cette thèse, des mesures en régime statique et en bruit ont été effectuées sur
des transistors FinFETs réalisés sur substrat SOI, issus de la technologie 32nm, ayant deux …

The C shape behavior of the floating body effect in function of temperature in PD SOI nMOSFETs

PG Agopian, JAA Martino, E Simoen… - ECS Transactions, 2007 - iopscience.iop.org
The temperature influence on the gate induced floating body effect in partially depleted (PD)
Silicon-on-Insulator (SOI) nMOSFETs is investigated, through experimental results and two …

[PDF][PDF] The “C” Shape Behavior of the Gate Induced Floating Body Effect in function of temperature in PD SOI nMOSFETs

PG Der Agopian, JA Martino, E Simoen, C Claeys - Citeseer
The temperature influence on the gate induced floating body effect in partially depleted (PD)
Silicon-on-Insulator (SOI) nMOSFETs is investigated, through experimental results and two …

Estudo do comportamento de transistores de tunelamento induzido por efeito de campo (TFET) operando em diferentes temperaturas.

CCM Bordallo - 2017 - teses.usp.br
Neste trabalho iniciou-se os estudos com transistores de tunelamento por efeito de campo
(TFET) de silício (Si) em estruturas de nanofios (NW-TFET), analisando o efeito da redução …

Simulations of transient behavior and parasitic effects for 20 nm gate length of PD SOI nMOSFET

F Rehman, HB Jin, JB Li, A Bukhtiar, M Khalid… - Materials Today …, 2015 - Elsevier
In this paper, we report the possible transient behavior for 20 nm partially depleted silicon-
on-insulator (PD SOI) n-channel MOSFET studied using Synopsys TCAD program …