Method of making three dimensional NAND memory
N Mokhlesi, R Scheuerlein - US Patent 7,575,973, 2009 - Google Patents
(57) ABSTRACT A method of making a monolithic, three dimensional NAND string including
a first memory cell located over a second memory cell, includes growing a semiconductor …
a first memory cell located over a second memory cell, includes growing a semiconductor …
Three dimensional NAND memory
N Mokhlesi, R Scheuerlein - US Patent 7,848,145, 2010 - Google Patents
(57) ABSTRACT A monolithic, three dimensional NAND string includes a first memory cell
located over a second memory cell, a select transistor, a first word line of the first memory …
located over a second memory cell, a select transistor, a first word line of the first memory …
Thermal annealing in hydrogen for 3-D profile transformation on silicon-on-insulator and sidewall roughness reduction
A fast, effective process using hydrogen annealing is introduced to perform profile
transformation on silicon-on-insulator (SOI) and to reduce sidewall roughness on silicon …
transformation on silicon-on-insulator (SOI) and to reduce sidewall roughness on silicon …
Method of making three dimensional NAND memory
N Mokhlesi, R Scheuerlein - US Patent 7,514,321, 2009 - Google Patents
US7514321B2 - Method of making three dimensional NAND memory - Google Patents
US7514321B2 - Method of making three dimensional NAND memory - Google Patents …
US7514321B2 - Method of making three dimensional NAND memory - Google Patents …
Three dimensional nand memory
N Mokhlesi, R Scheuerlein - US Patent 7,851,851, 2010 - Google Patents
(57) ABSTRACT A monolithic, three dimensional NAND string includes a first memory cell
located over a second memory cell. A semicon ductor active region of the first memory cell is …
located over a second memory cell. A semicon ductor active region of the first memory cell is …
Electrical characteristics of 20-nm junctionless Si nanowire transistors
We have fabricated n-channel junctionless nanowire transistors with gate lengths in the
range of 20–250nm, and have compared their electrical performances with conventional …
range of 20–250nm, and have compared their electrical performances with conventional …
Low-frequency noise in silicon-on-insulator devices and technologies
An overview is given on the low-frequency (LF) noise of silicon-on-insulator (SOI) devices
and technologies. In the first two parts, noise mechanisms specific for SOI are discussed …
and technologies. In the first two parts, noise mechanisms specific for SOI are discussed …
Method of making three dimensional NAND memory
N Mokhlesi, R Scheuerlein - US Patent 7,808,038, 2010 - Google Patents
(57) ABSTRACT A monolithic, three dimensional NAND string includes a first memory cell
located over a second memory cell. A semicon ductor active region of the first memory cell is …
located over a second memory cell. A semicon ductor active region of the first memory cell is …
Method of making three dimensional NAND memory
N Mokhlesi, R Scheuerlein - US Patent 7,745,265, 2010 - Google Patents
(57) ABSTRACT A method of making a monolithic, three dimensional NAND string, includes
forming a select transistor, forming a first memory cell over a second memory cell, forming a …
forming a select transistor, forming a first memory cell over a second memory cell, forming a …
Improvement of FinFET electrical characteristics by hydrogen annealing
W Xiong, G Gebara, J Zaman… - IEEE Electron …, 2004 - ieeexplore.ieee.org
Hydrogen anneal is used during FinFET processing to round off the corners of the silicon
fins prior to gate oxidation and to smooth the surface of the fin sidewalls. This procedure …
fins prior to gate oxidation and to smooth the surface of the fin sidewalls. This procedure …