[PDF][PDF] Multi-objective Pareto frontand particle swarm optimization algorithms for power dissipation reduction in microprocessors

DR Sulaiman - International Journal of Electrical and Computer …, 2020 - core.ac.uk
The progress of microelectronics making possible higher integration densities, and a
considerable development of on-board systems are currently undergoing, this growth comes …

Design of a low power CMOS inverter with the VBB stack approach

S Khmailia, J Rouabeh, A Mami - Engineering, Technology & Applied …, 2022 - etasr.com
Due to the exponential advancement in nanotechnology devices, low energy consumption
has become a significant concern of researchers and VLSI designers. In this paper, the …

Memory and I/O optimized rectilinear Steiner minimum tree routing for VLSI

NR Latha, GR Prasad - International Journal of Electronics …, 2020 - igi-global.com
As the size of devices are scaling down at rapid pace, the interconnect delay play a major
part in performance of IC chips. Therefore minimizing delay and wire length is the most …

Framework for the Integration of Transmission Optimization Components into LoRaWAN Stack

B Mendes, S du Plessis, D Passos… - … and Intelligent Systems …, 2022 - Springer
The Internet of things has grown in recent years, and new applications are now emerging,
many requiring long-range coverage and low energy consumption while operating on low …

[PDF][PDF] A hybrid image similarity measure based on a new combination of different similarity techniques

NR Hamza, RA Dihin, MH Abdulameer - International Journal of …, 2020 - academia.edu
Image similarity is the degree of how two images are similar or dissimilar. It computes the
similarity degree between the intensity patterns in images. A new image similarity measure …

[PDF][PDF] Energy efficient improved content addressable memory using quantum-dot cellular automata

S Kotte, GK Durga - International Journal of Electrical and Computer …, 2024 - academia.edu
Quantum-dot cellular automata (QCA) is an emerging technology with high integration
density, low power consumption, and high operating speed. This study introduces a QCA …

Design of Low-Power Parallel Prefix Adder Templates Using Asynchronous Techniques

J Sudhkar, EJ Rao - … and Intelligent Systems: Proceedings of ICCIS 2021, 2022 - Springer
This paper aims to design low-power circuits like an adder, buffer, AOI, and logic gates using
asynchronous quasi delay insensitive (QDI) templates, essential for many arithmetic …

Forced stack sleep transistor (FORTRAN): a new leakage current reduction approach in CMOS based circuit designing

SR Kassa, NK Misra, R Nagaria - Facta Universitatis, Series …, 2021 - casopisi.junis.ni.ac.rs
Reduction in leakage current has become a significant concern in nanotechnology-based
low-power, low-voltage, and high-performance VLSI applications. This research article …

Optimization of leakage power consumption in D Flip-Flop using hybrid technique

A Prakash, P Jain - Advances in AI for Biomedical Instrumentation …, 2024 - taylorfrancis.com
In deep submicron regime high performance digital circuits, leakage power accounts for a
sizable fraction of the total power consumption. An idle circuit only experiences leakage as a …

Optimization of Leakage Power Dissipation in CMOS Inverter using Self biased and W/L Scaling Techniques

A Prakash, P Jain - 2023 2nd International Conference on …, 2023 - ieeexplore.ieee.org
Now a day's due to the rapid development of nanoscale device, low power dissipation has
grown to be a serious problem for researchers and VLSI designers. We are presenting the …