Fuzz, penetration, and ai testing for soc security verification: Challenges and solutions
The ever-increasing usage and application of system-on-chips (SoCs) has resulted in the
tremendous modernization of these architectures. For a modern SoC design, with the …
tremendous modernization of these architectures. For a modern SoC design, with the …
Sharpen: Soc security verification by hardware penetration test
As modern SoC architectures incorporate many complex/heterogeneous intellectual
properties (IPs), the protection of security assets has become imperative, and the number of …
properties (IPs), the protection of security assets has become imperative, and the number of …
EnSAFe: enabling sustainable SoC security auditing using eFPGA-based accelerators
The utilization of reconfigurable and flexible acceleration for compute-intensive kernels, eg,
neural networks, crypto-engines, and arithmetics, have been on the rise in recent years …
neural networks, crypto-engines, and arithmetics, have been on the rise in recent years …
PSC-watermark: power side channel based IP watermarking using clock gates
With the ever-increasing re-use of intellectual property (IP) cores in modern system-on-chips
(SoCs), it is crucial to prevent security risks such as IP piracy and overuse. Considering that …
(SoCs), it is crucial to prevent security risks such as IP piracy and overuse. Considering that …
LLE: mitigating IC piracy and reverse engineering by last level edit
S Rahman, N Varshney, F Farahmandi… - … for Testing and …, 2023 - dl.asminternational.org
Hardware obfuscation is a proactive design-for-trust technique against integrated circuit (IC)
supply chain threats, ie, intellectual property (IP) piracy and overproduction. Many studies …
supply chain threats, ie, intellectual property (IP) piracy and overproduction. Many studies …
A Zero Trust-based framework employed by Blockchain Technology and Ring Oscillator Physical Unclonable Functions for security of Field Programmable Gate Array …
A Kulkarni, NA Hazari, M Niamat - IEEE Access, 2024 - ieeexplore.ieee.org
The field programmable gate array (FPGA) supply chain is vulnerable to security issues from
untrusted participants involved, resulting in the significant research being conducted in this …
untrusted participants involved, resulting in the significant research being conducted in this …
Adaptive PUF design to authenticate and evaluate heterogeneous IPs in edge computing
S Hemavathy, J Kokila… - The Journal of …, 2024 - Springer
Edge computing has become quintessential in commercial, healthcare, and industrial
applications. It enables real-time data processing at the edge device, thus reducing the data …
applications. It enables real-time data processing at the edge device, thus reducing the data …
CAPEC: A Cellular Automata Guided FSM-based IP Authentication Scheme
The ever-increasing propensity for intellectual property (IP) reuse has reduced the design
productivity gap in the supply chain. As a consequence, protecting IPs has become more …
productivity gap in the supply chain. As a consequence, protecting IPs has become more …
Rtl-fsmx: Fast and accurate finite state machine extraction at the rtl for security applications
At the early stage of the design process, many security vulnerability assessment solutions
require fast and precise extraction of the finite state machines (FSMs) present in the register …
require fast and precise extraction of the finite state machines (FSMs) present in the register …
GEM-water: generation of em-based watermark for SoC IP validation with hidden FSMs
Intellectual property (IP) core reuse is a common practice for accelerating new product
development in modern system-on-chip (SoC) architectures. However, reusing and sharing …
development in modern system-on-chip (SoC) architectures. However, reusing and sharing …