Voltjockey: Breaching trustzone by software-controlled voltage manipulation over multi-core frequencies

P Qiu, D Wang, Y Lyu, G Qu - Proceedings of the 2019 ACM SIGSAC …, 2019 - dl.acm.org
ARM TrustZone builds a trusted execution environment based on the concept of hardware
separation. It has been quite successful in defending against various software attacks and …

Reliable on-chip systems in the nano-era: Lessons learnt and future trends

J Henkel, L Bauer, N Dutt, P Gupta, S Nassif… - Proceedings of the 50th …, 2013 - dl.acm.org
Reliability concerns due to technology scaling have been a major focus of researchers and
designers for several technology nodes. Therefore, many new techniques for enhancing and …

Soft error susceptibilities of 22 nm tri-gate devices

N Seifert, B Gill, S Jahinuzzaman… - … on Nuclear Science, 2012 - ieeexplore.ieee.org
We report on measured radiation-induced soft error rates (SER) of memory and logic
devices built in a 22 nm high-k metal gate bulk Tri-Gate technology. Our results demonstrate …

Physics of multiple-node charge collection and impacts on single-event characterization and soft error rate prediction

JD Black, PE Dodd, KM Warren - IEEE Transactions on Nuclear …, 2013 - ieeexplore.ieee.org
Physical mechanisms of single-event effects that result in multiple-node charge collection or
charge sharing are reviewed and summarized. A historical overview of observed circuit …

Processor design for soft errors: Challenges and state of the art

T Li, JA Ambrose, R Ragel… - ACM Computing Surveys …, 2016 - dl.acm.org
Today, soft errors are one of the major design technology challenges at and beyond the
22nm technology nodes. This article introduces the soft error problem from the perspective …

Neutron-and proton-induced single event upsets for D-and DICE-flip/flop designs at a 40 nm technology node

TD Loveless, S Jagannathan, T Reece… - … on Nuclear Science, 2011 - ieeexplore.ieee.org
Neutron-and proton-induced single-event upset cross sections of D-and DICE-Flip/Flops are
analyzed for designs implemented in a 40 nm bulk technology node. Neutron and proton …

Clear: C ross-l ayer e xploration for a rchitecting r esilience-combining hardware and software techniques to tolerate soft errors in processor cores

E Cheng, S Mirkhani, LG Szafaryn, CY Cher… - Proceedings of the 53rd …, 2016 - dl.acm.org
We present a first of its kind framework which overcomes a major challenge in the design of
digital systems that are resilient to reliability failures: achieve desired resilience targets at …

Ionizing Radiation Effectsin Electronics

M Bagatin, S Gerardin - 2016 - api.taylorfrancis.com
There is an invisible enemy that constantly threatens the operation of electronics: ionizing
radiation. From sea level to outer space, ionizing radiation is virtually everywhere. At sea …

Delta DICE: A double node upset resilient latch

N Eftaxiopoulos, N Axelos, G Zervakis… - 2015 IEEE 58th …, 2015 - ieeexplore.ieee.org
In this paper we propose the novel Delta DICE latch that is tolerant to SNUs (Single Node
Upsets) and DNUs (Double Node Upsets). The latch comprises three DICE cells in a delta …

Design of robust SRAM cells against single-event multiple effects for nanometer technologies

R Rajaei, B Asgari, M Tabandeh… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
As technology size scales down toward lower two-digit nanometer dimensions, sensitivity of
CMOS circuits to radiation effects increases. Static random access memory cells (SRAMs) …