System level analysis of fast, per-core DVFS using on-chip switching regulators
W Kim, MS Gupta, GY Wei… - 2008 IEEE 14th …, 2008 - ieeexplore.ieee.org
Portable, embedded systems place ever-increasing demands on high-performance, low-
power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well …
power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well …
Self-optimizing memory controllers: A reinforcement learning approach
Efficiently utilizing off-chip DRAM bandwidth is a critical issuein designing cost-effective,
high-performance chip multiprocessors (CMPs). Conventional memory controllers deliver …
high-performance chip multiprocessors (CMPs). Conventional memory controllers deliver …
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth
DH Woo, NH Seong, DL Lewis… - HPCA-16 2010 The …, 2010 - ieeexplore.ieee.org
Memory bandwidth has become a major performance bottleneck as more and more cores
are integrated onto a single die, demanding more and more data from the system memory …
are integrated onto a single die, demanding more and more data from the system memory …
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
R Bitirgen, E Ipek, JF Martinez - 2008 41st IEEE/ACM …, 2008 - ieeexplore.ieee.org
Efficient sharing of system resources is critical to obtaining high utilization and enforcing
system-level performance objectives on chip multiprocessors (CMPs). Although several …
system-level performance objectives on chip multiprocessors (CMPs). Although several …
Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping
Phase change memory (PCM) is an emerging memory technology for future computing
systems. Compared to other non-volatile memory alternatives, PCM is more matured to …
systems. Compared to other non-volatile memory alternatives, PCM is more matured to …
Facelift: Hiding and slowing down aging in multicores
A Tiwari, J Torrellas - 2008 41st IEEE/ACM International …, 2008 - ieeexplore.ieee.org
Processors progressively age during their service life due to normal workload activity. Such
aging results in gradually slower circuits. Anticipating this fact, designers add timing …
aging results in gradually slower circuits. Anticipating this fact, designers add timing …
Resistive computation: Avoiding the power wall with low-leakage, STT-MRAM based computing
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit
microprocessor performance growth. To keep dynamic power constant across process …
microprocessor performance growth. To keep dynamic power constant across process …
Temperature-constrained power control for chip multiprocessors with online model estimation
As chip multiprocessors (CMP) become the main trend in processor development, various
power and thermal management strategies have recently been proposed to optimize system …
power and thermal management strategies have recently been proposed to optimize system …
Eddie: Em-based detection of deviations in program execution
This paper describes EM-Based Detection of Deviations in Program Execution (EDDIE), a
new method for detecting anomalies in program execution, such as malware and other code …
new method for detecting anomalies in program execution, such as malware and other code …
POSH: a TLS compiler that exploits program structure
As multi-core architectures with Thread-Level Speculation (TLS) are becoming better
understood, it is important to focus on TLS compilation. TLS compilers are interesting in that …
understood, it is important to focus on TLS compilation. TLS compilers are interesting in that …