An overview of efficient interconnection networks for deep neural network accelerators

SM Nabavinejad, M Baharloo, KC Chen… - IEEE Journal on …, 2020 - ieeexplore.ieee.org
Deep Neural Networks (DNNs) have shown significant advantages in many domains, such
as pattern recognition, prediction, and control optimization. The edge computing demand in …

NoC-based DNN accelerator: A future design paradigm

KC Chen, M Ebrahimi, TY Wang, YC Yang - Proceedings of the 13th …, 2019 - dl.acm.org
Deep Neural Networks (DNN) have shown significant advantages in many domains such as
pattern recognition, prediction, and control optimization. The edge computing demand in the …

Customizing clos network-on-chip for neural networks

R Hojabr, M Modarressi, M Daneshtalab… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
Large-scale neural network accelerators are often implemented as a many-core chip and
rely on a network-on-chip to manage the huge amount of inter-neuron traffic. The baseline …

Comparing the performance of multi-layer perceptron training on electrical and optical network-on-chips

F Dai, Y Chen, Z Huang, H Zhang, H Zhang… - The Journal of …, 2023 - Springer
Multi-layer perceptron (MLP) is a class of Artificial Neural Networks widely used in
regression, classification, and prediction. To accelerate the training of MLP, more cores can …

Reconfigurable network-on-chip based convolutional neural network accelerator

A Firuzan, M Modarressi, M Reshadi… - Journal of Systems …, 2022 - Elsevier
Abstract Convolutional Neural Networks (CNNs) have a wide range of applications due to
their superior performance in image and pattern classification. However, the performance of …

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

Y Aydi, S Mnejja, FQ Mohammed, M Abid - Applied Sciences, 2023 - mdpi.com
In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a
promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and …

A high-performance network-on-chip topology for neuromorphic architectures

N Akbari, M Modarressi - 2017 IEEE international conference …, 2017 - ieeexplore.ieee.org
Emerging neural network accelerators are often implemented as many-core chips and rely
on a network-on-chip to handle the huge amount of inter-neuron traffic. The wellknown mesh …

DiaNet: An efficient multi-grained re-configurable neural network in silicon

R Zhang, Y Chen, T Nakada… - 2019 32nd IEEE …, 2019 - ieeexplore.ieee.org
A hardware friendly topology of neural network is proposed in this work. Instead of full
connections between neighbor layers, the bisection-propagation from “parents” to “twins” is …

VS-ISA: A video specific instruction set architecture for ASIP design

Z Shen, H He, Y Zhang, Y Sun - 2006 International Conference …, 2006 - ieeexplore.ieee.org
This paper describes a novel video specific instruction set architecture for ASIP design. With
SIMD (Single Instruction Multiple Data) instructions, and video specific instructions, an …