A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor
SS Mukherjee, C Weaver, J Emer… - … . 36th Annual IEEE …, 2003 - ieeexplore.ieee.org
Single-event upsets from particle strikes have become a key challenge in microprocessor
design. Techniques to deal with these transients faults exist, but come at a cost. Designers …
design. Techniques to deal with these transients faults exist, but come at a cost. Designers …
Evaluating mapreduce for multi-core and multiprocessor systems
C Ranger, R Raghuraman, A Penmetsa… - 2007 IEEE 13th …, 2007 - ieeexplore.ieee.org
This paper evaluates the suitability of the MapReduce model for multi-core and multi-
processor systems. MapReduce was created by Google for application development on data …
processor systems. MapReduce was created by Google for application development on data …
SWIFT: Software implemented fault tolerance
To improve performance and reduce power, processor designers employ advances that
shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates …
shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates …
[图书][B] VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …
design a testable and quality product, drive down test cost, improve product quality and …
An overview of radiation effects on electronic devices under severe accident conditions in NPPs, rad-hardened design techniques and simulation tools
New requirements on post-accident monitoring systems in nuclear power plants pose fresh
challenges for electronic system designers and nuclear power plant personnel, in particular …
challenges for electronic system designers and nuclear power plant personnel, in particular …
Detection and correction of silent data corruption for large-scale high-performance computing
Faults have become the norm rather than the exception for high-end computing clusters.
Exacerbating this situation, some of these faults remain undetected, manifesting themselves …
Exacerbating this situation, some of these faults remain undetected, manifesting themselves …
[图书][B] Architecture design for soft errors
S Mukherjee - 2011 - books.google.com
Architecture Design for Soft Errors provides a comprehensive description of the architectural
techniques to tackle the soft error problem. It covers the new methodologies for quantitative …
techniques to tackle the soft error problem. It covers the new methodologies for quantitative …
The soft error problem: An architectural perspective
SS Mukherjee, J Emer… - … Symposium on High …, 2005 - ieeexplore.ieee.org
Radiation-induced soft errors have emerged as a key challenge in computer system design.
If the industry is to continue to provide customers with the level of reliability they expect …
If the industry is to continue to provide customers with the level of reliability they expect …
Robust system design with built-in soft-error resilience
Transient errors caused by terrestrial radiation pose a major barrier to robust system design.
A system's susceptibility to such errors increases in advanced technologies, making the …
A system's susceptibility to such errors increases in advanced technologies, making the …
Shoestring: Probabilistic soft error reliability on the cheap
Aggressive technology scaling provides designers with an ever increasing budget of
cheaper and faster transistors. Unfortunately, this trend is accompanied by a decline in …
cheaper and faster transistors. Unfortunately, this trend is accompanied by a decline in …