This work describes a 4-bit Flash ADC with low power consumption. The performance
metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence …

The design approaches for high-speed SAR ADCs are discussed in this work. It's an
interleaving architecture with a fast coarse successive approximation register quantizer and …

This work is based on a low power comparator design for SAR ADCs. The pre-amplifier uses
an inverter-based input pair with a floater reservoir capacitor to achieve both current reusing …

English In this work, a new architecture of Thermometer to Binary Encoder is designed in
45nm CMOS Technology for 4-bit FLASH ADC. The Thermometer code is converted to …

A new architecture for a low-power successive approximation register analog to digital
converter (SAR ADC) is presented in this paper. In addition to the channel, there is a fast …

In this work, an ascendable low power 64-bit priority encoder is designed using a two-
directional array to three-directional array conversion, and Split-logic technique and 6-bit is …