A method and system are provided for prefetching information in a processing system. A first
memory has multiple first locations. At least one of the first locations stores information …

US PATENT DOCUMENTS FOREIGN PATENT DOCUMENTS 5,666,553 A 9, 1997 Crozier
EP O8O1478 10, 1997 5,678,039 A 10, 1997 Hinks et al. JP 2000-20370 1, 2000 5,680,542 …

(57) ABSTRACT A method, for use in a processor context, wherein instructions in a program
executable are encoded with plural instruction set encodings. A method wherein a control …

4,403,303 A 9, 1983 Howes et al. 5,704,053 A 12/1997 Santhanam 4.410. 939 A 10, 1983
Kawakami 5,717.440 A* 2/1998 Katsura et al................. 345/558 4,434.461 A 2, 1984 Puhl …

US PATENT DOCUMENTS is scheduled later than in the first instruction Schedule. The first
basic block of instructions is rescheduled by determin 4,435,756 3/1984 …

57 ABSTRACT A high-performance, SuperScalar-based computer System with out-of-order
instruction execution for enhanced resource utilization and performance throughput. The …

57 ABSTRACT A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a
branch unit that cooperate to detect when the target of a branch (designated a short branch) …

57 ABSTRACT A microprocessor (50) includes a main central process ing unit (CPU)(70)
and a separate direct memory access (DMA) CPU (72) in a single integrated circuit making …

BACKGROUND OF THE INVENTION The present invention involves an apparatus for exe
cuting instructions in a computing device. In particular, the present invention provides an …

BACKGROUND OF THE INVENTION One of the fundamental goals in any computer system
architecture is to minimize the time the system takes to complete a given task. This …